Highly Linear Analog Spike Processing Block Integrated With an AND-Type Flash Array and CMOS Neuron Circuits

Lee, Kyu-Ho; Kwon, Dongseok; Woo, Sung Yun; Ko, Jong Hyun; Choi, Woo Young; Park, Byung‐Gook; Lee, Jong‐Ho

doi:10.1109/ted.2022.3207707

Cited by 5 publications

(5 citation statements)

References 34 publications

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“…Here, we adopt a complementary metal‐oxide‐semiconductor (CMOS) I&F neuron circuit previously reported by our group. [ 8 ] The mechanism of the I&F neuron circuit is represented as follows. The current sum copied by the current mirror flows into the membrane capacitor of the neuron circuit, changing the gate voltage of the M 1 transistor.…”

Section: Architecture Of Analog Spiking Neural Network Hardwarementioning

confidence: 99%

“…In the subsequent section, we aim to verify the performance estimation of our developed SNNSim. Building upon our preceding research, [ 8 ] we have fabricated single‐layer analog SNNs with CMOS I&F neuron circuits integrated with a charge‐trapping flash array. We initially fit the electrical characteristics of the fabricated devices with the existing metal oxide semiconductor field effect transistor (MOSFET) model in the SPICE simulation.…”

Section: Validationmentioning

confidence: 99%

“…To date, numerous studies have employed fully analog systems with analog synapses and integrate-and-fire (I&F) neurons to implement SNNs. [8][9][10] However, it remains unclear how such a fully analog SNN would perform in terms of area, accuracy, latency, and power consumption when it is implemented in large-scale. Due to their ability to significantly reduce computational resources, analog SNNs present a promising option for serving as a substitutional processor in edge computing and on-device computing.…”

Section: Introductionmentioning

confidence: 99%

“…The contributions of this work can be summarized as follows: 1) We design analog SNNs using nonvolatile flash memory devices and I&F neurons to be extended to the multi-layer networks, in contrast to the reported works focusing on the single-layer SNN. [8][9][10] 2) We develop SNNSim that enables accurate and fast simulations of customized analog SNNs that reflect specifications of synaptic devices and neuron circuits. 3) We analyze and optimize the performance of the analog SNNs through the SNNSim, including area overhead, latency and verify the ultra-energy-efficiency as well as high accuracy of bio-inspired analog SNNs.…”

Section: Introductionmentioning

confidence: 99%

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SNNSim: Investigation and Optimization of Large‐Scale Analog Spiking Neural Networks Based on Flash Memory Devices

Ko,

Kwon,

Hwang

et al. 2024

Advanced Intelligent Systems

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Spiking neural networks (SNNs) have emerged as a novel approach for reducing computational costs by mimicking the biologically plausible operations of neurons and synapses. In this article, large‐scale analog SNNs are investigated and optimized at the hardware‐level by using SNNSim, the novel simulator for SNNs that employ analog synaptic devices and integrate‐and‐fire (I&F) neuron circuits. SNNSim is a reconfigurable simulator that accurately and very quickly models the behavior of the user‐defined device characteristics and returns key metrics such as area, accuracy, latency, and power consumption as output. Notably, SNNSim exhibits exceptional efficiency, as it can process the entire 10 000 Modified National Institute of Standards and Technology (MNIST) test dataset in a few seconds, whereas SPICE simulations require hours to simulate a single MNIST test data. Using SNNSim, the conversion of artificial neural networks (ANNs) to SNNs is simulated and the performance of the large‐scale analog SNNs is optimized. The results enable the design of accurate, high‐speed, and low‐power operation of large‐scale SNNs. SNNSim code is now available at https://github.com/SMDLGITHUB/SNNSim.

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Section: Architecture Of Analog Spiking Neural Network Hardwarementioning

confidence: 99%

Section: Validationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

SNNSim: Investigation and Optimization of Large‐Scale Analog Spiking Neural Networks Based on Flash Memory Devices

Ko,

Kwon,

Hwang

et al. 2024

Advanced Intelligent Systems

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“…1A). Moreover, according to Kirchhoff's and Ohm's laws, NC architectures perform massively parallel operations with high energy efficiency and reduced area overhead (19)(20)(21)(22)(23).…”

Section: Introductionmentioning

confidence: 99%

Reconfigurable neuromorphic computing block through integration of flash synapse arrays and super-steep neurons

et al. 2023

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Neuromorphic computing (NC) architecture inspired by biological nervous systems has been actively studied to overcome the limitations of conventional von Neumann architectures. In this work, we propose a reconfigurable NC block using a flash-type synapse array, emerging positive feedback (PF) neuron devices, and CMOS peripheral circuits, and integrate them on the same substrate to experimentally demonstrate the operations of the proposed NC block. Conductance modulation in the flash memory enables the NC block to be easily calibrated for output signals. In addition, the proposed NC block uses a reduced number of devices for analog-to-digital conversions due to the super-steep switching characteristics of the PF neuron device, substantially reducing the area overhead of NC block. Our NC block shows high energy efficiency (37.9 TOPS/W) with high accuracy for CIFAR-10 image classification (91.80%), outperforming prior works. This work shows the high engineering potential of integrating synapses and neurons in terms of system efficiency and high performance.

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NOR-Type Flash Array Based on Four-Terminal TFT Synaptic Devices Capable of Selective Program/Erase Exploiting Fowler-Nordheim Tunneling

Hwang,

Park,

Kang

et al. 2024

IEEE Electron Device Lett.

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Highly Linear Analog Spike Processing Block Integrated With an AND-Type Flash Array and CMOS Neuron Circuits

Cited by 5 publications

References 34 publications

SNNSim: Investigation and Optimization of Large‐Scale Analog Spiking Neural Networks Based on Flash Memory Devices

SNNSim: Investigation and Optimization of Large‐Scale Analog Spiking Neural Networks Based on Flash Memory Devices

Reconfigurable neuromorphic computing block through integration of flash synapse arrays and super-steep neurons

NOR-Type Flash Array Based on Four-Terminal TFT Synaptic Devices Capable of Selective Program/Erase Exploiting Fowler-Nordheim Tunneling

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