Higher Radix and Redundancy Factor for Floating Point SRT Division

Anane, M.; Bessalah, H.; Issad, Mohamed; Anane, N.; Salhi, Hassen

doi:10.1109/tvlsi.2008.2000363

Cited by 11 publications

(15 citation statements)

References 4 publications

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“…However, in the R4HV-CORDIC algorithm, the selection criteria to choose the are complex and depend on both coordinate values and . The convergence of the R4HV-CORDIC can be derived using the SRT-division method as given in 27 , 28 . According to the SRT division, the variable is converted into a new variable as .…”

Section: Modified Radix-4 Cordicmentioning

confidence: 99%

Radix-4 CORDIC algorithm based low-latency and hardware efficient VLSI architecture for Nth root and Nth power computations

Changela,

Kumar,

Woźniak

et al. 2023

Sci Rep

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In this article, a low-complexity VLSI architecture based on a radix-4 hyperbolic COordinate Rotion DIgital Computer (CORDIC) is proposed to compute the $$N{{\rm th}}$$ N th root and $$N{{\rm th}}$$ N th power of a fixed-point number. The most recent techniques use the radix-2 CORDIC algorithm to compute the root and power. The high computation latency of radix-2 CORDIC is the primary concern for the designers. $$N{{\rm th}}$$ N th root and $$N{{\rm th}}$$ N th power computations are divided into three phases, and each phase is performed by a different class of the proposed modified radix-4 CORDIC algorithms in the proposed architecture. Although radix-4 CORDIC can converge faster with fewer recurrences, it demands more hardware resources and computational steps due to its intricate angle selection logic and variable scale factor. We have employed the modified radix-4 hyperbolic vectoring (R4HV) CORDIC to compute logarithms, radix-4 linear vectoring (R4LV) to perform division, and the modified scaling-free radix-4 hyperbolic rotation (R4HR) CORDIC to compute exponential. The criteria to select the amount of rotation in R4HV CORDIC is complicated and depends on the coordinates $$X^j$$ X j and $$Y^j$$ Y j of the rotating vector. In the proposed modified R4HV CORDIC, we have derived the simple selection criteria based on the fact that the inputs to R4HV CORDIC are related. The proposed criteria only depend on the coordinate $$Y^j$$ Y j that reduces the hardware complexity of the R4HV CORDIC. The R4HR CORDIC shows the complex scale factor, and compensation of such scale factor necessitates the complex hardware. The complexity of R4HR CORDIC is reduced by pre-computing the scale factor for initial iterations and by employing scaling-free rotations for later iterations. Quantitative hardware analysis suggests better hardware utilization than the recent approaches. The proposed architecture is implemented on a Virtex-6 FPGA, and FPGA implementation demonstrates $$19\%$$ 19 % less hardware utilization with better error performance than the approach with the radix-2 CORDIC algorithm.

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Section: Modified Radix-4 Cordicmentioning

confidence: 99%

Radix-4 CORDIC algorithm based low-latency and hardware efficient VLSI architecture for Nth root and Nth power computations

Changela,

Kumar,

Woźniak

et al. 2023

Sci Rep

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show abstract

“…Compared with the classical SRT divider, the proposed divider needs additional partial quotient digits correction circuit, multiplier k selection circuit and the partial remainder correction circuit in the data path. According to the description in (17), in the proposed divider, the partial quotient digits correction circuit can be realized by a simpler subtractor with 4-bit and one operand is fixed to 1, moreover, the partial quotient digits correction circuit is not included in the data path of iterative calculation. However, the multiplier k selection circuit and partial remainder correction circuit shown in Figure 1 will increase the delay of iterative calculation path and reduce the circuit performance.…”

Section: Proposed Divider Architecturementioning

confidence: 99%

“…As an example, a radix-16 SRT divider was proposed in [17], in which 53.3kb ROM is required to implement the QDS table. Due to the large area cost of the QDS table, low-radix SRT algorithm is normally implemented in area-sensitive embedded microprocessor cores.…”

Section: Introductionmentioning

confidence: 99%

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An Architecture of Area-Effective High Radix Floating-Point Divider With Low-Power Consumption

2021

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In this paper, a novel architecture of area-effective high-radix floating-point divider with low power consumption is proposed. By extending the principle of the standard SRT algorithm, the divider can estimate the partial quotient digits by a simpler circuit and tolerate certain calculation errors in each recurrence cycle. In addition, the accumulation of errors in the recurrence process can be eliminated automatically without additional calculation cycle. The latency and area cost of the divider are linear with the radix number, which solves the problem that the quotient digits selection tables in high-radix divider have high area cost. Base on the proposed architecture a single-precision floating-point divider is implemented, which has an area of 6037.20um 2 in 65nm process. The dynamic power consumption of the divider is only 0.848mW at 250MHz. Compared with other dividers reported in the literature, the area cost can be reduced by about 90% with the same computation precision and performance.INDEX TERMS High-radix, division, SRT, quotient-digits-selection.

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“…The two most well-known digit-recurrence algorithms are SRT [Srinivas and Parhi 1995;Anane et al 2008] and CORDIC algorithm [Alachiotis 2011a;Zhou et al 2008;Muller 2006], which are implemented with simple addition and shift operations. However, both are linearly convergent and a fixed number of bits are obtained from each iteration.…”

Section: Introductionmentioning

confidence: 99%

FPGA Implementation of a Special-Purpose VLIW Structure for Double-Precision Elementary Function

Lei

Guo

Dou

et al. 2014

ACM Trans. Reconfigurable Technol. Syst.

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In the current article, the capability and flexibility of field programmable gate-arrays (FPGAs) to implement IEEE-754 double-precision floating-point elementary functions are explored. To perform various elementary functions on the unified hardware efficiently, we propose a special-purpose very long instruction word (VLIW) processor, called DP VELP. This processor is equipped with multiple basic units, and its performance is improved through an explicitly parallel technique. Pipelined evaluation of polynomial approximation with Estrin's scheme is proposed, by scheduling basic components in an optimal order to avoid data hazard stalls and achieve minimal latency. The custom VLIW processor can achieve high scalability. Under the control of specific VLIW instructions, the basic units are combined into special-purpose hardware for elementary functions. Common elementary functions are presented as examples to illustrate the design of elementary function in DP VELP in detail. Minimax approximation scheme is used to reduce degree of polynomial. Compromise between the size of lookup table and the latency is discussed, and the internal precision is carefully planned to guarantee accuracy of the result. Finally, we create a prototype of the DP VELP unit and an FPGA accelerator based on the DP VELP unit on a Xilinx XC6VLX760 FPGA chip to implement the SGP4/SDP4 application.Compared with previous researches, the proposed design can achieve low latency with a reasonable amount of resources and evaluate a variety of elementary functions with the unified hardware to satisfy the demands in scientific applications. Experimental results show that the proposed design guarantees more than 99% of correct rounding. Moreover, the SGP4/SDP4 accelerator, which is equipped with 39 DP VELP units and runs at 200 MHz, outperforms the parallel software approach with hyper-thread technology on an Intel Xeon Quad E5620 CPU at 2.40 GHz by a factor of 7X. . 2014. FPGA implementation of a special-purpose VLIW structure for double-precision elementary function.

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Higher Radix and Redundancy Factor for Floating Point SRT Division

Cited by 11 publications

References 4 publications

Radix-4 CORDIC algorithm based low-latency and hardware efficient VLSI architecture for Nth root and Nth power computations

Radix-4 CORDIC algorithm based low-latency and hardware efficient VLSI architecture for Nth root and Nth power computations

An Architecture of Area-Effective High Radix Floating-Point Divider With Low-Power Consumption

FPGA Implementation of a Special-Purpose VLIW Structure for Double-Precision Elementary Function

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