An Architecture of Area-Effective High Radix Floating-Point Divider With Low-Power Consumption

Yang, Yuheng; Yuan, Qing; Liu, Jian

doi:10.1109/access.2021.3065063

Cited by 3 publications

(1 citation statement)

References 29 publications

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“…In fact, RAPID bears a great potential to be deployed in the mantissa multiplier/divider which consume more than 95% of the total area and power in the floating point unit (in which division latency is up to 35× of addition operation) [20,73]. Recently, this track has attracted noticeable attention, especially due to the ever-growing usage of 3D computer graphics [74,75].…”

Section: Discussionmentioning

confidence: 99%

RAPID: Approximate Pipelined Soft Multipliers and Dividers for High Throughput and Energy Efficiency

Ebrahimi

Zaid

Wijtvliet

et al. 2023

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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The rapid updates in error-resilient applications along with their quest for high throughput has motivated designing fast approximate functional units for Field-Programmable Gate Arrays (FPGAs). Studies have proposed various imprecise functional techniques, albeit posed with three shortcomings: first, most existing inexact multipliers and dividers are specialized for Application-Specific Integrated Circuit (ASIC) platforms. Therefore, due to the architectural differences of underlying building blocks in FPGA and ASIC, ASIC-customized designs have not yielded comparable improvements when directly synthesized and ported to FPGAs. Second, state-of-the-art (SoA) approximate units are substituted, mostly in a single kernel of a multi-kernel application. Moreover, the end-to-end assessment is adopted on the Quality of Results (QoR), but not on the overall gained performance. Finally, existing imprecise components are not designed to support a pipelined approach, which could boost the operating frequency/throughput of, e.g., divisionincluded applications. In this paper, we propose RAPID, the first pipelined approximate multiplier and divider architectures, customized for FPGAs. The proposed units efficiently utilize 6-input Look-up Tables (6-LUTs) and fast carry chains to implement Mitchell's approximate algorithms. Our novel error-refinement scheme not only has negligible overhead over the baseline Mitchell's approach, but also boosts its accuracy to 99.4% for arbitrary size of multiplication and division.Experimental results obtained with Xilinx Vivado demonstrate the efficiency of the proposed pipelined and non-pipelined RAPID multipliers and dividers over accurate counterparts. In particular, 4-stage pipelined architecture of 32-bit RAPID multiplier (divider) enables 3.3× (5.1×) higher throughput, 2.3× (6.8×) higher throughput/Watt, and 52% (31%) savings of LUTs, over their 4-stage pipelined, accurate IP counterparts. Moreover, the end-to-end evaluations of non-pipelined RAPID, deployed in three multi-kernel applications in the domains of bio-signal processing, image processing, and moving object tracking for Unmanned Air Vehicles (UAV) indicate up to 35%, 33%, and 45% improvements in area, latency, and Area-Delay-Product (ADP), respectively, over accurate kernels, with negligible loss in QoR. To springboard future research in reconfigurable and approximate computing communities, our implementations will be available and open-sourced at https://cfaed.tu-dresden.de/pd-downloads.

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