RAPID: Approximate Pipelined Soft Multipliers and Dividers for High Throughput and Energy Efficiency

Abstract

The rapid updates in error-resilient applications along with their quest for high throughput has motivated designing fast approximate functional units for Field-Programmable Gate Arrays (FPGAs). Studies have proposed various imprecise functional techniques, albeit posed with three shortcomings: first, most existing inexact multipliers and dividers are specialized for Application-Specific Integrated Circuit (ASIC) platforms. Therefore, due to the architectural differences of underlying building blocks in FPGA and ASIC, ASIC-customized designs have not yielded comparable improvements when directly synthesized and ported to FPGAs. Second, state-of-the-art (SoA) approximate units are substituted, mostly in a single kernel of a multi-kernel application. Moreover, the end-to-end assessment is adopted on the Quality of Results (QoR), but not on the overall gained performance. Finally, existing imprecise components are not designed to support a pipelined approach, which could boost the operating frequency/throughput of, e.g., divisionincluded applications. In this paper, we propose RAPID, the first pipelined approximate multiplier and divider architectures, customized for FPGAs. The proposed units efficiently utilize 6-input Look-up Tables (6-LUTs) and fast carry chains to implement Mitchell's approximate algorithms. Our novel error-refinement scheme not only has negligible overhead over the baseline Mitchell's approach, but also boosts its accuracy to 99.4% for arbitrary size of multiplication and division.Experimental results obtained with Xilinx Vivado demonstrate the efficiency of the proposed pipelined and non-pipelined RAPID multipliers and dividers over accurate counterparts. In particular, 4-stage pipelined architecture of 32-bit RAPID multiplier (divider) enables 3.3× (5.1×) higher throughput, 2.3× (6.8×) higher throughput/Watt, and 52% (31%) savings of LUTs, over their 4-stage pipelined, accurate IP counterparts. Moreover, the end-to-end evaluations of non-pipelined RAPID, deployed in three multi-kernel applications in the domains of bio-signal processing, image processing, and moving object tracking for Unmanned Air Vehicles (UAV) indicate up to 35%, 33%, and 45% improvements in area, latency, and Area-Delay-Product (ADP), respectively, over accurate kernels, with negligible loss in QoR. To springboard future research in reconfigurable and approximate computing communities, our implementations will be available and open-sourced at https://cfaed.tu-dresden.de/pd-downloads.

Analysis of Approximate adders with single functional error

“…At the system architecture level, approximate accelerators and programmable processors have been developed to improve an architecture [5]. Circuit-level approximation techniques reduce the power dissipation of circuits by simplifying basic arithmetic units, such as full adders [6][7][8][9][10][11][12][13][14][15][16] and multipliers [17][18][19][20]. Approximate storage techniques include implementing different refresh rates for different DRAMs [21] and applying voltage scaling to SRAMs [22,23].…”