Optimization and Implementation of SR T -16 Floating-Point Divider Based on FPGA

Zhou, Xi; Shen, Ruibing; He, Pengju; Gao, Han

doi:10.1109/ainit61980.2024.10581736

2024 5th International Seminar on Artificial Intelligence, Networking and Information Technology (AINIT) 2024

DOI: 10.1109/ainit61980.2024.10581736

|View full text |Cite

Optimization and Implementation of SR T -16 Floating-Point Divider Based on FPGA

Xi Zhou,

Ruibing Shen,

Pengju He

et al.

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...

Citation Types

Supporting

Mentioning

Contrasting

Publication Types

Select...

Relationship

Self Cite0

Independent0

Authors

Journals

Cited by 0 publications

References 11 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

No citations

Set email alert for when this publication receives citations?

scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.

Contact Info

hi@scite.ai

10624 S. Eastern Ave., Ste. A-614

Henderson, NV 89052, USA

Blog Terms and Conditions API Terms Privacy Policy Contact Cookie Preferences Do Not Sell or Share My Personal Information

Made with 💙 for researchers

Part of the Research Solutions Family.

Optimization and Implementation of SR T -16 Floating-Point Divider Based on FPGA

Cited by 0 publications

References 11 publications

No citations

Contact Info

Product

Resources

About