Higher Order Noise-Shaping Filters for High-Performance Micromachined Accelerometers

2017

A micromechanical capacitive accelerometer system is analyzed in this paper, which includes a high-Q sensing element and a high-order switched-capacitor (SC) sigma-delta ΣΔ CMOS interface circuit. The high-Q high-order topology obtained a sub-µg/√Hz noise floor. The loop stability is implemented by the operation of electrostatic feedback force, heavy phase compensation and the off-chip adjusting of distributed-feedback factors. The interface circuit is implemented in a standard 0.5 µm CMOS process. The system consumes 12 mW from a single 5 V supply with the noise level of lower than 400 ng/√Hz. The system bandwidth is 600 Hz and the input range of the accelerometer is ²0.7 g. The measured sensitivity of 2.5 V/g is achieved.

Section: Measurement Resultsmentioning

confidence: 99%

“…The element sensor parameters depend on Ref. [7], and the interface parameters are decided by calculation and Matlab simulation [8].…”

Section: Sensing Element and Systemmentioning

confidence: 99%

Design analysis of a high-Q micromechanical capacitive accelerometer system

2017

“…2 presents the interface circuit diagram of micromechanical AEÁ accelerometer in detail which consists of charge sensitization, correlated-double-sampling (CDS) and hold circuit, lead compensator, AEÁ modulator, 3-bit quantizer, 3 bits-DAC and linearization circuit. CDS is accomplished to eliminate feed through and lead compensator is used to ensure the stability of overall system [8]. Electrostatic feedback and charge sensitization are accomplished in different phases in one cycle, which greatly eliminates feed through between feedback signal and pick-up charge signal.…”

Section: Proposed Architecturementioning

confidence: 99%

A high performance with low harmonic distortion interface circuit of sigma-delta accelerometer

Liu

et al. 2016

A high performance interface circuit of sigma-delta accelerometer with low harmonic distortion used many kinds of circuit processing techniques is presented in this work. Multi-bit, dynamic element matching, correlated-double-sampling and electrostatic force feedback linearization circuit are used simultaneously in order to achieve the design indicators. Because of the usage of multi-bit, the design to operational amplifier (OPA) becomes easier, and only a single-stage folded-cascode amplifier is used in the modulator, the OSR is only 64. It highly reduced the difficulty of circuit. The test results indicate that the chip area is only about 10 mm 2 and the power dissipation is 10 mW with a sampling frequency of 60 kHz. The dynamic range (DR) of the system can be lower than −130 dB, the SNR and SNDR reach to −120 dB and −110 dB respectively with a resolution about 17 bits when referred to 3g full scale DC acceleration under CMOS 0.5 µm process. The dc nonlinearity of it is 0.2%. This paper realizes an approach which can both simplify the design of the interface circuit and improve the performance of it.

“…The stability of high-order system is an important problem for both AEÁ A/D converters and accelerometers, and there is no precise analytic approach to ascertain the stability of a modulator without resorting to simulation [9]. Stability is difficult to achieve for a high-order AEÁ electromechanical modulator due to the increased number of poles in the loop filter [7].…”

Section: Stabilitymentioning

confidence: 99%

A high-order sigma-delta accelerometer interface circuit

Liu

et al. 2015

A high-order high-Q closed-loop sigma-delta (ΣΔ) capacitive microaccelerometer interface circuit is presented in this work. The quantization noise in baseband of the interface circuit is greatly suppressed by a highorder loop shaping, and the mechanical noise is deceased by the use of a vacuum-packaged sensor element. A lead compensator is used to damp the high-Q element to guarantee a stable high-order system. The interface circuit is implemented in a standard CMOS process, and the power dissipation is 10 mW from a 5 V supply and sampling frequency of 250 kHz. The highorder high-Q closed-loop ΣΔ capacitive microaccelerometer has a noise floor of 5 µg/Hz 1/2 with bandwidth of 600 Hz.