A high-order sigma-delta accelerometer interface circuit

Li, Xiangyu; Chen, Weiping; Liu, Xiaowei; Ren, Mingyuan

doi:10.1587/elex.12.20141035

Cited by 4 publications

(4 citation statements)

References 9 publications

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“…The accelerometer is fully superior to the previous research presented in [4] which is quantified by 1-bit quantizer. …”

Section: Resultsmentioning

confidence: 83%

“…A high performance inertial sensor as described in previous paper [4], which uses a AEÁ topology interface to form closed-loop control system, has strict requirements on the output SNR/SNDR. This paper will introduce an interface circuit AEÁ accelerometer with not only low noise advantage but also low harmonics distortion property.…”

Section: Proposed Architecturementioning

confidence: 99%

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A high performance with low harmonic distortion interface circuit of sigma-delta accelerometer

Chen

Liu

et al. 2016

IEICE Electron. Express

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A high performance interface circuit of sigma-delta accelerometer with low harmonic distortion used many kinds of circuit processing techniques is presented in this work. Multi-bit, dynamic element matching, correlated-double-sampling and electrostatic force feedback linearization circuit are used simultaneously in order to achieve the design indicators. Because of the usage of multi-bit, the design to operational amplifier (OPA) becomes easier, and only a single-stage folded-cascode amplifier is used in the modulator, the OSR is only 64. It highly reduced the difficulty of circuit. The test results indicate that the chip area is only about 10 mm 2 and the power dissipation is 10 mW with a sampling frequency of 60 kHz. The dynamic range (DR) of the system can be lower than −130 dB, the SNR and SNDR reach to −120 dB and −110 dB respectively with a resolution about 17 bits when referred to 3g full scale DC acceleration under CMOS 0.5 µm process. The dc nonlinearity of it is 0.2%. This paper realizes an approach which can both simplify the design of the interface circuit and improve the performance of it.

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“…The accelerometer is fully superior to the previous research presented in [4] which is quantified by 1-bit quantizer. …”

Section: Resultsmentioning

confidence: 83%

Section: Proposed Architecturementioning

confidence: 99%

A high performance with low harmonic distortion interface circuit of sigma-delta accelerometer

Chen

Liu

et al. 2016

IEICE Electron. Express

Self Cite

View full text Add to dashboard Cite

show abstract

“…However, extra power was induced by designing an extra oscillator, and the PWM signal had to be converted into a digital signal again for digital signal processing (DSP). To directly output a digital signal, a ∆Σ feedback loop approach [10][11][12][13][14]17] was proposed. In this approach, conventional integrators designed with operational trans-conductance amplifiers (OTAs) are commonly used.…”

Section: Introductionmentioning

confidence: 99%

“…To overcome the above-mentioned nonlinearity induced by the mismatch with a simpler topology, a pulse width modulation force (PWM) or ΔΣ feedback loop approach in [ 10 , 11 , 12 , 13 , 14 , 15 , 16 ] is presented. These are able to eliminate the nonlinearity in voltage-to-force transduction.…”

Section: Introductionmentioning

confidence: 99%

A Bond-Wire Drift Offset Minimized Capacitance-to-Digital Interface for MEMS Accelerometer with Gain-Enhanced VCO-Based Quantization and Nested Digital Chopping Feedback Loops

Yin

Yang

2021

Sensors

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This paper presents an output offset minimized capacitance-to-digital interface for a MEMS accelerometer. With a gain-enhanced voltage-controlled oscillator (VCO)-based quantization loop, the interface is able to output a digital signal with improved dynamic range. For optimizing the output offset caused by nonideal factors (e.g., the bond-wire drift), a nested digital chopping feedback loop is embedded in the VCO-based quantization loop. It enables the interface to minimize the output offset without digital filtering and digital-to-analog conversion. The proposed architecture is well suited for dynamic range and offset improvements with low cost. Fabricated with a 0.18 μm Global Foundry (GF) CMOS process, the interface offers a 78 dB dynamic range with 0.4% nonlinearity from a single 2 V supply. With the input referred offset up to 1.3 pF, the offset cancellation loop keeps the DC output offset within 40 mV. The power dissipation is 6.5 mW with a bandwidth of 4 kHz.

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Study of a three-axis digital tunneling resistance-type magnetic sensor

Yin

Chen

et al. 2016

IEICE Electron. Express

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In this paper, an interface circuit for a three-axis digital tunneling resistance-type magnetic sensor in a standard 0.5 µm CMOS technology is presented. The weak signal detection is achieved by the chopper instrumentation amplifier. The conversion between analog and digital is achieved by the fully differential fourth-order forward Sigma-Delta modulator. The output zero-bias of magnetic sensor is corrected by digital auto-offset circuit. The design and fabrication of tunneling resistance-type magnetic sensor interface ASIC with digital output have been achieved by the research. The performance of magnetic sensor is shown as below: the sensor is at 5 V operating voltage, the value of consumption is only 120 mW; the nonlinear of the sensor is 0.1%FS; the zero reference output is less than 10 nT; the equivalent input noise density is less than 0.13 nT/Hz 1/2 (at 10 Hz).

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A high-order sigma-delta accelerometer interface circuit

Cited by 4 publications

References 9 publications

A high performance with low harmonic distortion interface circuit of sigma-delta accelerometer

A high performance with low harmonic distortion interface circuit of sigma-delta accelerometer

A Bond-Wire Drift Offset Minimized Capacitance-to-Digital Interface for MEMS Accelerometer with Gain-Enhanced VCO-Based Quantization and Nested Digital Chopping Feedback Loops

Study of a three-axis digital tunneling resistance-type magnetic sensor

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