High Volume and Fast Turnaround Automated Inline TEM Sample Preparation for Manufacturing Process Monitoring

Kang, Hyoung H.; King, J.F.; Patterson, Oliver D.; Herschbein, Steven B.; Nadeau, James P.; Fuller, Scott E.

doi:10.31399/asm.cp.istfa2010p0102

Cited by 2 publications

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“…'Wafer return' is a possible workflow for the manufacture of microelectronics that attracted attention in the last decade [1][2][3][4][5][6]. It allows us to continue wafer processing after analysis with a focused ion beam (FIB) for local cross sectional scanning electron microscopy (SEM), the extraction of lamellae for in situ low-kV scanning transmission electron microscopy (STEM) or off-line TEM/STEM analysis.…”

Section: Introductionmentioning

confidence: 99%

Surface contamination and electrical damage by focused ion beam: conditions applicable to the extraction of TEM lamellae from nanoelectronic devices

Bender

Franquet

Drijbooms

et al. 2015

Semicond. Sci. Technol.

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Focused ion beams (FIBs) are widely applied during manufacturing and for failure analysis, as a preparation tool for cross sectional scanning electron microscopy or for the extraction of lamellae for (scanning) transmission electron microscopy investigation of nanoelectronic devices. The impact of the ion beam milling on surface contamination is investigated by time-of-flight secondary ion mass spectroscopy, while the electrical surface damage is analyzed by a micro four-point probe. It is shown that the redeposition of milled Ga and Cu reaches levels below sensitivity (5 × 10 10 at cm −2 ) at less than 10 mm from FIB structures while the lateral range of electrical surface damage is an order of magnitude smaller. The major source of the redeposition is the resputtering of sputtered material from the sample that was previously deposited on the SEM column. The 2D distribution of the redeposition is asymmetric and is simulated well based on a simplified model of the column and sample configuration. The electrical surface damage mainly relates to the beam tails. Pt deposits for surface protection require much lower Ga + ion doses, and therefore have less impact on the wafer surface contamination. However, the range of electrical surface damage is larger for Pt deposits due to increased beam scattering in the low vacuum during the Pt deposition. With these contamination and damage levels and ranges, 'wafer return', i.e. continuing the wafer processing after the FIB, can be considered feasible for back-end of line processes with the loss of only the analyzed die or, potentially, also its neighbor. For front-end of line processes the acceptable contamination levels are more stringent and the feasibility of wafer return will be more process specific.

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