High Transconductance Gain Current Differencing Transconductance Amplifiers Using a New Approach of gm Boosting

Kour, Raviraj; Pandey, Rishikesh; Kumar, Shireesh

doi:10.1007/s11277-021-08187-8

Cited by 4 publications

(2 citation statements)

References 30 publications

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“…By applying positive V BG , the I OFF is further suppressed to be ≈0.11 pA due to the reduction of the kinetic energy of electrons, the I ON increases up to 4.58 µA attributing to an increase in the electron density in bottom MoS 2 layer. As shown in Figure 3d, the maximum transconductance ( G max ) is also increased with bottom gate at V DS of 2 V, reaching up to 15.14 µS, which is twice as high as that at V BG = 0 V. In previous reports, the transconductance was usually raised by increasing the bias voltage, but at the expense of power consumption, [ 62–64 ] our transistor then provides a power‐efficient way to tune the G max using an additional gate knob. As the bottom gate increases, the V T gradually shifts from negative to positive (from −0.17 to 0.58 V), indicating the bottom gate has great regulation on the electrical transport barrier in the top‐gated transistor.…”

Section: Resultsmentioning

confidence: 60%

2D Short‐Channel Tunneling Transistor Relying on Dual‐Gate Modulation for Integrated Circuits Application

Deng

Sun

et al. 2023

Adv Funct Materials

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With continuous size scaling, the surface dangling bonds and short‐channel effects will degrade silicon based transistor performance. Thus, it is of great importance to seek new channel materials and transistor architectures to further continue Moore's law. Herein, a new ultra‐thin short‐channel tunneling transistor is developed comprising all 2D‐ components. Distinct from usual 2D planar transistor, this device is configured with vertical MoS2/WSe2 junction and in‐plane WSe2 channel, the switch states are realized by the gate‐regulated barrier height of heterojunction, enabling the transition of transport mechanism between thermionic‐emission and tunneling. Under dual‐gate configuration, the transistor exhibits high performance with drive current of 4.58 µA, on/off ratio of 4 × 107, subthreshold swing (SS) of 97 mV decade−1 and drain‐induced barrier lowering (DIBL) of 12 mV V−1, that can meet the requirement of logical applications in integrated circuits (IC). Taking advantage of the high‐speed tunneling current and unique short‐channel architecture, the device overcomes the issues of voltage spikes and long reverse recovery time that exist in usual electric components, and thus gains an access to the IC interface. This work provides a proof‐of‐concept transistor architecture relying on dual‐gate modulation, opening up a promising perspective for next generation low‐power, high‐density, and large‐scale IC technologies.

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Section: Resultsmentioning

confidence: 60%

2D Short‐Channel Tunneling Transistor Relying on Dual‐Gate Modulation for Integrated Circuits Application

Deng

Sun

et al. 2023

Adv Funct Materials

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“…The VDTA block is a newly introduced building block derived from the Current Differencing Transconductance Amplifier (CDTA) [22]. Front-end current differential unit is exchanged with a voltage differencing unit in VDTA [23].…”

Section: Description Of Vdta Circuitmentioning

confidence: 99%

VDTA Based Transadmittance Mode Instrumentation Amplifier with Experimental results

Raj

Dutta

Ranjan

et al. 2023

Preprint

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A Voltage Differencing Transconductance Amplifier (VDTA) based trans-admittance mode (TAM) instrumentation amplifier (IA) has been proposed in this article. Proposed IA provides electronically tunable gain with biasing current along with high bandwidth (BW) and CMRR. In addition, the proposed IA does not need any resistor matching. An offset of the presented amplifier circuit can be suppressed using an integrator feedback stage. The functional verification is performed using 0.18 µm TSMC process parameter. Monte Carlo Sampling (MCS) is carried out, thus proving robustness of the circuit. As an application part, a noisy ECG signal is applied to get a clean amplified signal. A CMRR of 131dB-146.8 dB has been obtained depending on different values of the components, and biasing conditions. 30 MHz bandwidth is obtained for the proposed IA. The IA layout required 80 × 49 µm2 areas. The experimental verification has been done using commercially available ICs CA3080.

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Differential high gain transimpedance amplifier with –3dB-bandwidth extension

Hosseini

Mohammadnejad

Karami

2023

Microelectronics Journal

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High Transconductance Gain Current Differencing Transconductance Amplifiers Using a New Approach of gm Boosting

Cited by 4 publications

References 30 publications

2D Short‐Channel Tunneling Transistor Relying on Dual‐Gate Modulation for Integrated Circuits Application

2D Short‐Channel Tunneling Transistor Relying on Dual‐Gate Modulation for Integrated Circuits Application

VDTA Based Transadmittance Mode Instrumentation Amplifier with Experimental results

Differential high gain transimpedance amplifier with –3dB-bandwidth extension

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