High-throughput bayesian computing machine with reconfigurable hardware

Abstract

We use reconfigurable hardware to construct a high throughput Bayesian computing machine (BCM) capable of evaluating probabilistic networks with arbitrary DAG (directed acyclic graph) topology. Our BCM achieves high throughput by exploiting the FPGA's distributed memories and abundant hardware structures (such as long carry-chains and registers), which enables us to 1) develop an innovative memory allocation scheme based on a maximal matching algorithm that completely avoids memory stalls, 2) optimize and deeply pipeline the logic design of each processing node, and 3) schedule them optimally. The BCM architecture not only can be applied to many important algorithms in artificial intelligence, signal processing, and digital communications, but also has high reusability, i.e., a new application needs not change a BCM's hardware design, only new task graph processing and code compilation are necessary. Moreover, the throughput of a BCM scales almost linearly with the size of the FPGA on which it is implemented.A Bayesian computing machine with 16 processing nodes was implemented with a Virtex-5 FPGA (XCV5LX155T-2) on a BEE3 (Berkeley Emulation Engine) platform. For a wide variety of sample Bayesian problems, comparing running the same network evaluation algorithm on a 2.4 GHz Core 2 Duo Intel processor and a GeForce 9400m using the CUDA software package, the BCM demonstrates 80x and 15x speedups respectively, with a peak throughput of 20.4 GFLOPS (Giga Floating-Point Operations per Second).

GraphGen: An FPGA Framework for Vertex-Centric Graph Computation

“…In comparison to prior FPGA-based graph computation frameworks [1][4] [6], GraphGen is unique because it is the only one that supports all of these features: (1) read and write operation on the graph data, (2) the use of off-chip DRAMs to manage the increasingly large graph dataset in modern graph-based applications, (3) an automated end-to-end compilation flow starting from a high-level vertex-centric specification to an FPGA implementation, and (4) support for multiple FPGA platforms.…”

XtokaxtikoX: A stochastic computing-based autonomous cyber-physical system

“…Nevertheless, stochastic computing has been applied to a limited set of applications which include DSP applications: Finite Impulse Response (FIR) and Infinite Impulse Response (IIR) filters [2], [3], neuromorphic and bioinspired systems: binary synapses for low-power neuromorphic systems [4], digital neurosynaptic network for neuromorphic chips to develop brain-like computational structures [5], decoding of Low-Density Parity Code (LDPC) codes [6], [7], and Bayesian computing machines [8]. Most of these applications are based on additions and multiplications, and are tolerant to some errors in their computations.…”

“…Stochastic computing has been applied to design many applications which include: digital filters FIR [10], IIR [2], neural networks [11][12], decoding of error correcting LDPC codes [6], [7], high-throughput Bayesian computing machines [8], and probabilistic neural networks [13], [12].…”

ASTRO: Synthesizing application-specific reconfigurable hardware traces to exploit memory-level parallelism

“…Techniques such as identifying ''hot'' (computationally intensive) binary traces (code segments) and consequentially synthesizing them into co-processor-like IP blocks [5], have been extensively studied. In fact, prior studies have frequently resulted in order-of-magnitude higher overall performance compared to CPU-or even GPU-based platforms [6,7]. More encouragingly, FPGA's advantages, over time, have become even more pronounced as the computing power of a single FPGA has continued to scale, whereas ASIC design and manufacturing costs have dramatically increased with each technology scaling.…”