High-Speed Serial AER on FPGA

Berge, Hans Kristian Otnes; Häfliger, Philipp

doi:10.1109/iscas.2007.378041

Cited by 32 publications

(23 citation statements)

References 6 publications

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“…Instead of the measures 58.56 Mevent/s of our prototype, in order to compare with the raw speed considered in other works, if only the transmission phase is considered, the maximum transmission speed is around 117 Mevent/s, same order of magnitude of other previous works [10,11,12]; however it is still far from the bandwidth obtained in the FACETS multilayer wafer scale neuromorphic system [18,6].…”

Section: Implementation Experimental Results and Discussionmentioning

confidence: 96%

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AER-SRT: Scalable spike distribution by means of synchronous serial ring topology address event representation

et al. 2016

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Given the massive number of interconnects in Spiking Neural Networks (SNNs), distributing spikes effciently becomes a critical issue for the efficient hardware emulation of large-scale SNNs. In this work, the AER-SRT (Address Event Representation over Synchronous Serial Ring Topology) architecture for spike transmission is proposed. AER-SRT is a light, easily scalable, packet-based solution implemented with high-speed serial link for multi-chip SNN communication. The channel uses a unidirectional, point-to-point connection between nodes, which provides a high transmission speed. Events (spikes) are distributed among all the nodes in a ring-topology pipeline fashion and the synchronous AER guarantees a collision-free scheme. The fast speed and efficient channel usage limits the spike distribution time to values that allow real-time operation for network sizes that can be calculated with simple design equations. Also, in the proposed communication protocol there is no specific or master node, so new nodes can be added to the ring by simply modifying two configuration parameters. As a proof of concept, a prototype of the architecture has been implemented and tested on FPGA development boards.

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Section: Implementation Experimental Results and Discussionmentioning

confidence: 96%

“…Serial AER utilizes fewer wires, exhibits better performance and does not limit the data word-width. Several serial AER systems have been reported in literature demonstrating better performance than traditional parallel bus [10,11,12,13].…”

Section: Introductionmentioning

confidence: 99%

AER-SRT: Scalable spike distribution by means of synchronous serial ring topology address event representation

et al. 2016

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“…The AER communication infrastructure we implemented uses serial differential signaling for inter-board communication, following an approach similar to the one proposed in [11].…”

Section: A General Trend Towards Serial Differential Signaling 1) Simentioning

confidence: 99%

“…The usage of such a SerDes chip allows us to get higher event rates at significant lower silicon cost. The FPGA and SerDes we use cost about $40, a about third of the cost for the cheapest Xilinx Virtex-II Pro series FPGA necessary for implementing a system as in [11]. Using this hardware we currently achieve event rates that are about three to four times faster than in [11].…”

Section: Serial Aer Interfacementioning

confidence: 99%

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A serial communication infrastructure for multi-chip address event systems

Fasnacht

Whatley

Indiveri

2008

2008 IEEE International Symposium on Circuits and Systems (ISCAS)

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In recent years there have been an increasing number of research groups that have begun to develop multi-chip address-event systems. The communication protocol used to transmit signals between these systems' components is based on the Address-Event Representation (AER). It is therefore important to have access to robust and reliable AER communication infrastructures for streamlining the systems' development and prototyping stages. We propose an AER communication infrastructure that can be easily interfaced to workstations or laptops during a prototyping phase, and that can be embedded into compact and low-cost systems in the application phase. The infrastructure proposed uses a novel serial AER interface with flow-control, overcomes many of the drawbacks observed with previous solutions, and can achieve event rates of up to 78.125MHz for 32bit AEs. Abstract-In recent years there have been an increasing number of research groups that have begun to develop multi-chip address-event systems. The communication protocol used to transmit signals between these systems' components is based on the Address-Event Representation (AER). It is therefore important to have access to robust and reliable AER communication infrastructures for streamlining the systems' development and prototyping stages.We propose an AER communication infrastructure that can be easily interfaced to workstations or laptops during a prototyping phase, and that can be embedded into compact and low-cost systems in the application phase. The infrastructure proposed uses a novel serial AER interface with flow-control, overcomes many of the drawbacks observed with previous solutions, and can achieve event rates of up to 78.125MHz for 32bit AEs.

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