We present an array of leaky integrate-and-fire (LIF) neuron circuits designed for the second-generation BrainScaleS mixed-signal 65-nm CMOS neuromorphic hardware. The neuronal array is embedded in the analog network core of a scaleddown prototype HICANN-DLS chip. Designed as continuoustime circuits, the neurons are highly tunable and reconfigurable elements with accelerated dynamics. Each neuron integrates input current from a multitude of incoming synapses and evokes a digital spike event output. The circuit offers a wide tuning range for synaptic and membrane time constants, as well as for refractory periods to cover a number of computational models. We elucidate our design methodology, underlying circuit design, calibration and measurement results from individual subcircuits across multiple dies. The circuit dynamics match with the behavior of the LIF mathematical model. We further demonstrate a winner-take-all network on the prototype chip as a typical element of cortical processing.
I . I N T R O D U C T I O NT HE architecture of digital microprocessors is fundamentally different from that of the central nervous system. While the brain is a massively parallel structure of neurons interconnected through synapses [1], microprocessors are mostly based on a von Neumann architecture [2], [3] with logic gates as the elementary primitives. The human brain consumes only approximately 20 W [4], while its performance as a generalpurpose problem solver is still unmatched by any computer algorithm.Taking inspiration from this biological feat, neuromorphic architectures not only adopt a non-von Neumann architecture by collocating memory close to the computational element, but also introduce massive parallelism, high energy efficiency, reconfigurability, fault tolerance, and integrate computational *Both authors contributed equally to this work.