High speed redundant self-correcting circuits for radiation hardened by design logic

Hindman, Nathan; Pettit, David E.; Patterson, Dan W.; Nielsen, Kyle E.; Yao, Xiaoyin; Holbert, Keith E.; Clark, Lawrence T.

doi:10.1109/radecs.2009.5994697

Cited by 9 publications

(4 citation statements)

References 16 publications

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“…Nevertheless, this solution does not address the SET effects nor the multi-bit upsets. The self-correcting TMR flipflops have been proposed in [45]- [47]. However, these solutions are highly customized, requiring partial modification of existing cells.…”

Section: State-of-the-art Solutions For Rad-hard Flip-flopsmentioning

confidence: 99%

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Design and Evaluation of Radiation-Hardened Standard Cell Flip-Flops

Schrape

Andjelković

Breitenreiter

et al. 2021

IEEE Trans. Circuits Syst. I

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Use of a standard non-rad-hard digital cell library in the rad-hard design can be a cost-effective solution for space applications. In this paper we demonstrate how a standard nonrad-hard flip-flop, as one of the most vulnerable digital cells, can be converted into a rad-hard flip-flop without modifying its internal structure. We present five variants of a Triple Modular Redundancy (TMR) flip-flop: baseline TMR flip-flop, latch-based TMR flip-flop, True-Single Phase Clock (TSPC) TMR flip-flop, scannable TMR flip-flop and self-correcting TMR flipflop. For all variants, the multi-bit upsets have been addressed by applying special placement constraints, while the Single Event Transient (SET) mitigation was achieved through the usage of customized SET filters and selection of optimal inverter sizes for the clock and reset trees. The proposed flip-flop variants feature differing performance, thus enabling to choose the optimal solution for every sensitive node in the circuit, according to the predefined design constraints. Several flip-flop designs have been validated on IHP's 130 nm BiCMOS process, by irradiation of custom-designed shift registers. It has been shown that the proposed TMR flip-flops are robust to soft errors with a threshold Linear Energy Transfer (LET) from (32.4 MeV• cm 2 mg ) to (62.5 MeV• cm 2 mg ), depending on the variant.

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Section: State-of-the-art Solutions For Rad-hard Flip-flopsmentioning

confidence: 99%

“…One solution is to place the majority voter inside a feedback loop in order to enable the self-correction in the slave stages. Approaches made of C-element/guard-gates are published in [45], [46], whereas a single extra latch is proposed in [47].…”

Section: Self-correcting Tmr Flip-flop (Sc-s-tmr)mentioning

confidence: 99%

Design and Evaluation of Radiation-Hardened Standard Cell Flip-Flops

Schrape

Andjelković

Breitenreiter

et al. 2021

IEEE Trans. Circuits Syst. I

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“…This technique works on the assumption that no two copies of the logic will be hit by the charged particle on the same node at the same time. With appropriate spatial separation of the key nodes, the probability is very low that it is almost impossible for such a case to occur [Hind09] [Hind11]. This technique can be in flip-flops after [Mavis02].…”

Section: Triple Modular Redundancymentioning

confidence: 99%

Redundant Skewed Clocking of Pulse-Clocked Latches for Low Power Soft Error Mitigation

Gujja

Chellappa

Ramamurthy

et al. 2015

2015 15th European Conference on Radiation and Its Effects on Components and Systems (RADECS)

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An integrated methodology combining redundant clock tree synthesis and pulse clocked latches mitigates both single event upsets (SEU) and single event transients (SET) with reduced power consumption. This methodology helps to change the hardness of the design on the fly. This approach, with minimal additional overhead circuitry, has the ability to work in three different modes of operation depending on the speed, hardness

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“…The Triple Modular Redundancy (TMR) technique is commonly adopted in the hardening design to correct the Single Event Upset (SEU) in sequential elements [2][3][4]. Because of its special redundancy design, TMR is considered immune to single event based on the assumption that only one node collects charge at some certain time.…”

Section: Introductionmentioning

confidence: 99%

Comparison of heavy-ion induced SEU for D- and TMR-flip-flop designs in 65-nm bulk CMOS technology

Chen

2014

Sci. China Inf. Sci.

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Heavy ion experiments were performed on D flip-flop (DFF) and TMR flip-flop (TMRFF) fabricated in a 65-nm bulk CMOS process. The experiment results show that TMRFF has about 92% decrease in SEU crosssection compared to the standard DFF design in static test mode. In dynamic test mode, TMRFF shows much stronger frequency dependency than the DFF design, which reduces its advantage over DFF at higher operation frequency. At 160 MHz, the TMRFF is only 3.2× harder than the standard DFF. Such small improvement in the SEU performance of the TMR design may warrant reconsideration for its use in hardening design.

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High speed redundant self-correcting circuits for radiation hardened by design logic

Cited by 9 publications

References 16 publications

Design and Evaluation of Radiation-Hardened Standard Cell Flip-Flops

Design and Evaluation of Radiation-Hardened Standard Cell Flip-Flops

Redundant Skewed Clocking of Pulse-Clocked Latches for Low Power Soft Error Mitigation

Comparison of heavy-ion induced SEU for D- and TMR-flip-flop designs in 65-nm bulk CMOS technology

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