Design and Evaluation of Radiation-Hardened Standard Cell Flip-Flops

Abstract

Use of a standard non-rad-hard digital cell library in the rad-hard design can be a cost-effective solution for space applications. In this paper we demonstrate how a standard nonrad-hard flip-flop, as one of the most vulnerable digital cells, can be converted into a rad-hard flip-flop without modifying its internal structure. We present five variants of a Triple Modular Redundancy (TMR) flip-flop: baseline TMR flip-flop, latch-based TMR flip-flop, True-Single Phase Clock (TSPC) TMR flip-flop, scannable TMR flip-flop and self-correcting TMR flipflop. For all variants, the multi-bit upsets have been addressed by applying special placement constraints, while the Single Event Transient (SET) mitigation was achieved through the usage of customized SET filters and selection of optimal inverter sizes for the clock and reset trees. The proposed flip-flop variants feature differing performance, thus enabling to choose the optimal solution for every sensitive node in the circuit, according to the predefined design constraints. Several flip-flop designs have been validated on IHP's 130 nm BiCMOS process, by irradiation of custom-designed shift registers. It has been shown that the proposed TMR flip-flops are robust to soft errors with a threshold Linear Energy Transfer (LET) from (32.4 MeV• cm 2 mg ) to (62.5 MeV• cm 2 mg ), depending on the variant.

Radiation Tolerant Multi-Bit Flip-Flop System With Embedded Timing Pre-Error Sensing

“…Typically, such bit upsets are automatically corrected through subsequent clock pulses or dedicated refresh cycles, or dedicated self-correcting designs are needed, like selfcorrecting delta-TMR [15]. The detection capability of the proposed system allows the system designer to use the ERROR signal to detect radiation strike event and provide refresh cycles to the system so that accumulation of errors can be avoided and good functionality of the system can be maintained.…”

“…We performed a comparative analysis on standalone FFs and microcontroller (MCU) implementation trials based on different FFs. Based on the same STD FF, 2-bit, 4-bit, and 8-bit even parity versions of the proposed system are implemented along with TMR and delta-TMR [15]. Simulations were caried out on all FFs to characterize various parameters of FFs under default working mode with no error condition.…”

“…Therefore, there is a sufficient margin for the typical operating range, which can be optimized with the help of timing pre-error detection, and OPP can be found. The LPTCHIP (30 mm 2 ) implemented in ST BCD 90 nm technology is based on multiple implementations of the same MCU, but with different FF variants, i.e., STD FF, DICE based FF [8], TMR FF [12,15], and the proposed multi-Bit FF system based on up to 2-bits of grouping with single buffer clock skew and common reset as shown in Fig. 3.…”

“…Its variant Delta TMR [13,14], based on temporal and spatial redundancy, deals with SET faults [2] along with SEU. Other TMR variants such as scannable TMR, latch-based TMR TSPC TMR, and self-correcting TMR, including delta TMR, were reported in [15], wherein delta TMR solution was found to be an effective rad-hard solution for space applications. Another self-correcting TMR solution called Temporal Self Voting Logic (TSVL) was reported in [16].…”

Guest Editorial: Special Issue Based on the 12th Edition of the Latin American Symposium on Circuits and Systems

“…In [3], Schrape et al demonstrate how a standard non-radhard flip-flop can be converted into a rad-hard flip-flop without modifying its internal structure. They present five variants of a triple modular redundancy (TMR) flip-flop.…”