High-speed parallel CRC circuits in VLSI

Pei, T.-B.; Zukowski, C.

doi:10.1109/26.141415

Cited by 147 publications

(68 citation statements)

References 2 publications

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“…This unfolding technique can be used to implement higher order parallelism which gives more speedup. But this technique has a drawback of higher fan-out as we increase the order of parallelism [10]. A more efficient technique called state-space transformation can be used to implement parallel CRC circuits [11].…”

Section: Crc Computation Techniquesmentioning

confidence: 99%

Cyclic Redundancy Checking (CRC) Accelerator for Embedded Processor Datapaths

Buzdar¹,

Sun²,

Kashif³

et al. 2017

ijacsa

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Abstract-We present the integration of a multimode Cyclic Redundancy Checking (CRC) accelerator unit with an embedded processor datapath to enhance the processor performance in terms of execution time and energy efficiency. We investigate the performance of CRC accelerated embedded processor datapath in terms of execution time and energy efficiency. Our evaluation shows that the CRC accelerated Microblaze SoftCore embedded processor datapath is 153 times more cycle and energy efficient than a datapath lacking a CRC accelerator unit. This acceleration is achieved at the cost of some area overhead.

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Section: Crc Computation Techniquesmentioning

confidence: 99%

Cyclic Redundancy Checking (CRC) Accelerator for Embedded Processor Datapaths

Buzdar¹,

Sun²,

Kashif³

et al. 2017

ijacsa

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“…Step by step, the register state value D 8 can be described as, In table 1, ⊕ is EXOR operation. Therefore, a parallel circuit structures are achieved for (2, 1, 5) convolutional encodes.…”

Section: Parallel Convulutional Encodesmentioning

confidence: 99%

“…Furthermore, the characters of more high speed computing and much less low power dissipation are needed for convolutional codes. Although many papers focus on parallel cyclic redundancy check (CRC) algorithm [8], these are not completely adapted to the convolutional encodes. So in this paper, we pay attentions to implementation of parallel convolutional encodes, which is proved to be a available method to approach more high speed computing and much less low power dissipation.…”

Section: Introductionmentioning

confidence: 99%

Design of (2, 1, N) Parallel Convolutional Encodes for VLSI

Duan

Huang

2013

AMM

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Abstract. The characters of more high speed computing and much less low power dissipation are needed to settle for convolutional encodes. In this paper, we present a parallel method for convolutional encodes with SMIC 0.35µm CMOS technology; hardware design and VLSI implementation of this algorithm are also presented. Use this method, parallel circuits structure can be easily designed, which take on excellent characters of more high speed computing and low power dissipation compared with traditional serial shift register structure for convolutional encodes.

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“…The parallel CRC algorithm in [1] processes an m -bit message in (m+k)/L clock cycles, where k is the order of the generator polynomial and L is the level of parallelism. However, in [2], m message bits can be processed in m/L clock cycles. High speed architectures for parallel long encoders are based on the multiplication and division computations on generator polynomial are efficient in terms of speeding up the parallel linear feedback shift register (LFSR) structures.…”

Section: Introductionmentioning

confidence: 99%