Cyclic Redundancy Checking (CRC) Accelerator for Embedded Processor Datapaths

Buzdar, Abdul Rehman; Sun, Liguo; Kashif, Rao; Azhar, Muhammad Waqar; Khan, Muhammad Imran

doi:10.14569/ijacsa.2017.080242

Cited by 2 publications

(1 citation statement)

References 8 publications

(9 reference statements)

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“…Secondly, when operating under identical timing constraints, it becomes evident that the ALU associated with an input signal exhibiting a toggling probability of 0.1 dissipates nearly twice as much power as its counterpart group. This discrepancy can be attributed to the fundamental principle that the toggling probability bears a direct proportionality to dynamic power, which, in turn, constitutes the predominant component of the overall power consumption (Khan et al, 2014a;2014b;Pedroni, 2020;Buzdar et al, 2017a;2017b). From Fig.…”

Section: Power Analysismentioning

confidence: 99%

Exploring the impact of initial design techniques on area, timing, and power in technology mapped designs: A case study on 32-bit arithmetic logic unit

Alshortan,

Almalaq,

Khan

2023

Int. j. adv. appl. sci.

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This research paper investigates the influence of different initial design techniques on the area, timing, and power aspects of technology-mapped designs. As a practical case study, we undertake the design and analysis of a 32-bit arithmetic logic unit (ALU) utilizing two distinct adder approaches. The ALU, a fundamental component of all processors, comprises three major units: the Adder responsible for signed and unsigned number addition and subtraction, the Logic unit which handles bitwise logical operations, and the Shifter unit facilitates arithmetic and logical shift operations. The two adder designs are based on the ripple carry method (ALU_RCA) and the Sklansky method (ALU_SKL), respectively. The design and analysis process involved utilizing established toolsets from Cadence, including NCSIM for simulation and verification, RTL Compiler for logic synthesis, static timing analysis and power estimation, and SOC encounter tool for floorplanning and layout. Through this investigation, we aim to shed light on the varying performance implications of different initial design approaches in technology-mapped designs.

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Section: Power Analysismentioning

confidence: 99%

Exploring the impact of initial design techniques on area, timing, and power in technology mapped designs: A case study on 32-bit arithmetic logic unit

Alshortan,

Almalaq,

Khan

2023

Int. j. adv. appl. sci.

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Harmonic Estimation and Comparative Analysis of Ultra-High Speed Flip-Flop and Latch Topologies for Low Power and High Performance Future Generation Micro-/Nano Electronic Systems

Khan

2023

ACM Trans. Des. Autom. Electron. Syst.

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This paper presents estimation and analysis of the higher order harmonics, power features, and real performance of flip-flop and master-slave latch topologies. This research article outlines the impact of transistor model quality and input signal selection on the estimate of higher order harmonic contents of switching waveform emitted by the digital integrated circuits. Highly integrated systems require accurate estimation of higher order harmonics to control noise. This work presents simulations of 12 kinds of flip-flop and latch topologies on different process technologies i.e., 28 nm, 45 nm, 65 nm, and 130 nm. It is implied that the steeper the spectrum roll-off, the fewer the contents of higher order harmonics. Results of 28 nm process design kit are improved compared to 45 nm, 65 nm, and 130 nm process design kits. Furthermore, the results of the comparison of representative flip-flop and latch topologies illustrate the advantage of the approach and the suitability for high performance and low power consumption.

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Cyclic Redundancy Checking (CRC) Accelerator for Embedded Processor Datapaths

Cited by 2 publications

References 8 publications

Exploring the impact of initial design techniques on area, timing, and power in technology mapped designs: A case study on 32-bit arithmetic logic unit

Exploring the impact of initial design techniques on area, timing, and power in technology mapped designs: A case study on 32-bit arithmetic logic unit

Harmonic Estimation and Comparative Analysis of Ultra-High Speed Flip-Flop and Latch Topologies for Low Power and High Performance Future Generation Micro-/Nano Electronic Systems

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