High Speed Max-Log-MAP Turbo SISO Decoder Implementation Using Branch Metric Normalization

Han, Juan; Erdogan, A.T.; Arslan, Tughrul

doi:10.1109/isvlsi.2005.37

Cited by 13 publications

(2 citation statements)

References 11 publications

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“…Though more configurations are possible, we use only two configurations, namely coded vs. uncoded, in our assessment of the use of coding in the ultra-low-power receiver design. Due to their high complexity and large power consumption, the state-of-the-art LDPC [22] and Turbo decoders [23] have low FOM decoder and are not suitable for an ultra-low-power receiver. We implemented and evaluated a Viterbi decoder [24] and a Hamming decoder [25] with different parameters.…”

Section: Acd Designmentioning

confidence: 99%

Receiver Design With an Adjustable Energy-Signal-Quality Tradeoff for IoT Networks

Detterer

Nabi

Jiao

et al. 2022

IEEE Internet Things J.

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Section: Acd Designmentioning

confidence: 99%

Receiver Design With an Adjustable Energy-Signal-Quality Tradeoff for IoT Networks

Detterer

Nabi

Jiao

et al. 2022

IEEE Internet Things J.

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“…The design in [24] shifts the normalization circuit, and the design in [25] applies the double state technique. However, it is a challenge to provide a stable clock signal with high frequency.…”

Section: B Critical Path Delaymentioning

confidence: 99%

Turbo Decoder Using Contention-Free Interleaver and Parallel Architecture

Wong

Lai

Lin

et al. 2010

IEEE J. Solid-State Circuits

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Abstract-This paper introduces a turbo decoder that utilizes multiple soft-in/soft-out (SISO) decoders to decode one codeword. In addition, each SISO decoder is modified to allow simultaneous execution over multiple successive trellis stages. The design issues related to the architecture with parallel high-radix SISO decoders are discussed. First, a contention-free interleaver for the hybrid parallelism is presented to overcome the complicated collision problem as well as reduce interconnection network complexity. Second, two techniques for the high-speed add-compare-select (ACS) circuits are given to lessen area overhead of the SISO decoder. Third, a modification of the processing schedule is made for higher operating efficiency. Two designs with parallel architecture have been implemented. The first design with 32 SISO decoders, each of which processes 2 symbols per cycle, has 160 Mb/s and 0.22 nJ/b/iter after measurement. The second design uses 16 SISO decoders to deal with 4 symbols per cycle and achieves 100% efficiency, leading to 1000 Mb/s and 0.15 nJ/b/iter in post-layout simulation.

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