Turbo Decoder Using Contention-Free Interleaver and Parallel Architecture

Abstract

Abstract-This paper introduces a turbo decoder that utilizes multiple soft-in/soft-out (SISO) decoders to decode one codeword. In addition, each SISO decoder is modified to allow simultaneous execution over multiple successive trellis stages. The design issues related to the architecture with parallel high-radix SISO decoders are discussed. First, a contention-free interleaver for the hybrid parallelism is presented to overcome the complicated collision problem as well as reduce interconnection network complexity. Second, two techniques for the high-speed add-compare-select (ACS) circuits are given to lessen area overhead of the SISO decoder. Third, a modification of the processing schedule is made for higher operating efficiency. Two designs with parallel architecture have been implemented. The first design with 32 SISO decoders, each of which processes 2 symbols per cycle, has 160 Mb/s and 0.22 nJ/b/iter after measurement. The second design uses 16 SISO decoders to deal with 4 symbols per cycle and achieves 100% efficiency, leading to 1000 Mb/s and 0.15 nJ/b/iter in post-layout simulation.

High performance parallel turbo decoder with configurable interleaving network for LTE application

“…Parallel decoding is employed which makes use of multiple soft-input soft-output (SISO) decoders to increase the throughput. Many studies [9][10][11][12][13][14][15][16] have been published to address the problem of initializing the recursion and simplify implementation of parallel decoding.…”

“…The rest state metrics to be estimated are calculated using the algorithm presented in [17]. The method to estimate initial values of forward recursion α of SISO 2s is NII instead of overlap in order to keep high operating efficiency [16]. Since the method to estimate initial values of effective backward recursion β of SISO 2s þ 1 does not affect operating efficiency, overlap method is adopted which is implemented by dummy backward recursion β d of SISO 2s þ 2.…”

A Novel Area-Efficient VLSI Architecture for Recursion Computation in LTE Turbo Decoders

“…β k (2) + γ k (6), β k (6) + γ k (7)}, (19) β k−2 (4) = max * {β k (3) + γ k (5), β k (7) + γ k (8),…”

High-throughput Contention-Free concurrent interleaver architecture for multi-standard turbo decoder

“…Parallel turbo decoding algorithms have been extensively investigated in the literature [5][6] [7] [8]. Most of these parallel decoding algorithms exploited SISO-decoder level parallelism, where the codeword (with block size K) is partitioned into P sub-blocks with the size of K/P .…”

“…(1) Design-time conflict resolutions usually jointly design the interleaving algorithm and the contention-free architectures [7][9] [16][17] [18]. These conflict resolutions employ dedicated interleaver architectures which can resolve the memory conflict problem for certain interleaving algorithms, which, however, lack flexibility to support other interleaving algorithms or existing systems such as HSPA+ and so on.…”