A Novel Area-Efficient VLSI Architecture for Recursion Computation in LTE Turbo Decoders

Abstract

Long term evolution (LTE) is aimed to achieve the peak data rates in excess of 300 Mb/s for the next generation wireless communication systems. Turbo codes, the specified channel coding scheme in LTE, suffer from a low-decoding throughput due to its iterative decoding algorithm. One efficient approach to achieve a promising throughput is to use multiple Maximum a-Posteriori (MAP) cores in parallel, resulting in a large area overhead. The two computationally challenging units in an MAP core are α and β recursion units. Although several methods have been proposed to shorten the critical path of these recursion units, their area-efficient architecture with minimum silicon area is still missing. In this paper, a novel relation existing between α and β metrics is introduced, leading to a novel add-compare-select (ACS) architecture. The proposed technique can be applied to both the precise approximation of log-MAP and max-log MAP ACS architectures. The proposed ACS design, implemented in a 0.13 µm CMOS technology and customized for the LTE standard, results in at most 18.1% less area compared to the reported designs to-date while maintaining the same throughput level.

Hardware Architecture of Layered Decoders for PLDPC-Hadamard Codes

“…Both turbo codes [1] and low-density parity-check (LDPC) codes [2] have been demonstrated to be capacity-approaching channel codes [3], [4]. They have been used in a wide variety of communication and data storage systems [5], including 3G/4G/5G cellular communications, optical communications, and magnetic recording systems, [6], [7], [8]; and various encoder/decoder designs have been proposed [9], [10], [11], [12]. In particular, turbo codes can employ the serial Bahl-Cocke-Jelinek-Raviv (BCJR) computational method in the iterative decoding algorithm to P.W.…”

Design of dual‐mode decoder based on LDPC/turbo code

“…Many communication standards chose the two codes as channel coding schemes. The excellent performance of LDPC and turbo codes enable the error correction decoder to play an important role in the communication between different networks [2]. However, the different decoding algorithms for LDPC and turbo codes usually lead to different hardware architectures.…”

A Novel Vector-Scalar Architecture for Mobile Baseband Processing

“…In Figure 1, the balance between flexibility and performance for all popular architectures is presented. The general single core processor has best flexibility but less performance power ratio and the ASIC has the best performance power ratio but less flexibility [4]. Software Defined Radio (SDR) baseband technology with high flexibility and low cost to upgrade is gradually replacing the traditional ASIC design method.…”