A 952MS/s Max-Log MAP Decoder Chip using Radix-4 × 4 ACS Architecture

Tang, Cheng-Hao; Wong, Cheng-Chi; Chen, Chih-Lung; Lin, Chien-Ching; Chang, Hsie-Chia

doi:10.1109/asscc.2006.357856

Cited by 17 publications

(11 citation statements)

References 7 publications

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“…We can see that the Radix-8 Log-MAP algorithm has nearly the same performance with Radix-4 Log-MAP algorithm, which proves it is feasible to incorporate three stages of state transitions together. Compared with the true Radix-8 Log-MAP algorithm, the proposed Radix-8 architecture has only a 0.03 dB performance loss at the BER of 10 -3 , it does as well as the Radix-8 Log-MAP algorithm when the BER is 10 -6 , while the Max-Log-MAP algorithm used in [8] have a 0.33 dB big loss at the BER of 10 -3 .…”

Section: B the Bit-error-rate(ber) Analysismentioning

confidence: 95%

“…C simulation models are built for four different kinds of turbo decoder in QPSK modulated AWGN channel: 1) the Radix-8 Max-Log-MAP algorithm used in [8]; 2) Radix-8 Log-MAP algorithm 3) Radix-4 Log-MAP algorithm 4) The Radix-8 algorithm presented in this paper.…”

Section: B the Bit-error-rate(ber) Analysismentioning

confidence: 99%

“…HSR8 eliminates the common metrics by subtraction according to the Radix-8 algorithmic traits; then moves the offset addition to the front end; carry-save (CS) structure is also used to reduce the computation delay according to [4]. To reduce hardware cost, two-dimensional method proposed in [8] is introduced, which reduces the number of branches from 8N to (4+2)N, where N is the number of state. The synthesis results show that the HSR8 can achieve a high throughput of 693Mbps while avoiding the area and the branch number increasing exponentially.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A Radix-8 Log-MAP recursion VLSI architecture

Jin¹,

Jian²,

Wang

et al. 2008

2008 11th IEEE International Conference on Communication Technology

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This paper presents a high speed Radix-8 Log-MAP turbo decoder recursion architecture: algorithmic approximation and architectural optimization are incorporated in the proposed designs to reduce the critical path. The synthesis results show that the proposed design has a high throughput of 693 Mbps in 0.18 um CMOS technology, which is nearly 3 times higher than using conventional Radix-2 architecture. The hardware complexity is only linearly increased with the new design. The simulation with AWGN channel shows that the proposed design has generally less than 0.05 dB performance degradation from the true Log-MAP decoder.

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Section: B the Bit-error-rate(ber) Analysismentioning

confidence: 95%

Section: B the Bit-error-rate(ber) Analysismentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A Radix-8 Log-MAP recursion VLSI architecture

Jin¹,

Jian²,

Wang

et al. 2008

2008 11th IEEE International Conference on Communication Technology

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“…To increase the throughput of SISO decoders, there are several methods such as the increase of parallelism of decoder [1][2][3][4][5][6][7][8][9][10], the improvement of operating frequency [11], and the high radix architecture [12][13][14]. This paper is focused on high operating frequency of radix-4 ACS unit for the high-throughput of radix-4 SISO decoders.…”

Section: Introductionmentioning

confidence: 99%

High Throughput Radix-4 SISO Decoding Architecture with Reduced Memory Requirement

Byun

Kim

Kim³

2014

JSTS:Journal of Semiconductor Technology and Science

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Abstract-As the high-throughput requirement in the next generation communication system increases, it becomes essential to implement high-throughput SISO (Soft-Input Soft-Output) decoder with minimal hardware resources. In this paper, we present the comparison results between cascaded radix-4 ACS (Add-Compare-Select) and LUT (Look-Up Table)based radix-4 ACS in terms of delay, area, and power consumption. The hardware overhead incurred from the retiming technique used for high speed radix-4 ACS operation is also analyzed. According to the various analysis results, high-throughput radix-4 SISO decoding architecture based on simple path metric recovery circuit is proposed to minimize the hardware resources. The proposed architecture is implemented in 65 nm CMOS process and memory requirement and power consumption can be reduced up to 78% and 32%, respectively, while achieving high-throughput requirement.

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“…Most of the works in the literature that propose radix-2 N T architectures are concerned to high throughput, and only a few explore the hardware complexity reduction. A radix-16 ACS unit to decompose the compare operation among 16 branches into two levels is presented in [6]. The hardware overhead is minimized thanks to a two-dimensional ACS unit architecture.…”

Section: Introductionmentioning

confidence: 99%

High speed low complexity radix-16 Max-Log-MAP SISO decoder

Sanchez

Jegoy

Jézéquel

et al. 2012

2012 19th IEEE International Conference on Electronics, Circuits, and Systems (ICECS 2012)

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International audienceAt present, the main challenge for hardware implementation turbo decoders is to achieve the high data rates required by current and future communication system standards. In order to address this challenge, a low complexity radix-16 SISO decoder for the Max-Log- MAP algorithm is proposed in this paper. Based on the elimination of parallel paths in the radix-16 trellis diagram, architectural solutions to reduce the hardware complexity of the different blocks of a SISO decoder are detailed. Moreover, two complementary techniques are introduced order to overcome BER/FER performance degradation when turbo decoders based on the proposed SISO decoder are considered. Thus, a penalty lower than 0.05dB is observed for a 8 state binary turbo code with respect to a traditional radix-2 turbo decoder for 6 decoding iterations

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A 952MS/s Max-Log MAP Decoder Chip using Radix-4 × 4 ACS Architecture

Cited by 17 publications

References 7 publications

A Radix-8 Log-MAP recursion VLSI architecture

A Radix-8 Log-MAP recursion VLSI architecture

High Throughput Radix-4 SISO Decoding Architecture with Reduced Memory Requirement

High speed low complexity radix-16 Max-Log-MAP SISO decoder

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