High speed low complexity radix-16 Max-Log-MAP SISO decoder

Abstract

International audienceAt present, the main challenge for hardware implementation turbo decoders is to achieve the high data rates required by current and future communication system standards. In order to address this challenge, a low complexity radix-16 SISO decoder for the Max-Log- MAP algorithm is proposed in this paper. Based on the elimination of parallel paths in the radix-16 trellis diagram, architectural solutions to reduce the hardware complexity of the different blocks of a SISO decoder are detailed. Moreover, two complementary techniques are introduced order to overcome BER/FER performance degradation when turbo decoders based on the proposed SISO decoder are considered. Thus, a penalty lower than 0.05dB is observed for a 8 state binary turbo code with respect to a traditional radix-2 turbo decoder for 6 decoding iterations

Revisiting the Max-Log-Map Algorithm With SOVA Update Rules: New Simplifications for High-Radix SISO Decoders

“…As already mentioned earlier, the merge path operation described above involves three procedures: 1) selecting the output path metric 2) selecting the related hard decision and 3) updating the related reliability value using function φ in (12). We show in this section that the merge operation has the commutative and associative properties.…”

“…For the commutative property, let us define p and p as in (9). The path metric of the output path is then M p , the hard decision is u p and according to (12), the reliability value is then equal to…”

“…Previous works in the literature, such as [10], [11], mainly tried to increase the throughput of BCJR-based SISO decoders, without specifically considering the complexity reduction of the studied algorithm. Only in [12], a low-complexity radix-16 SISO decoder for the MLM algorithm was proposed, with the introduction of specific processing to limit the resulting error correction degradation at high signal-to-noise ratios.…”

High Throughput Radix-4 SISO Decoding Architecture with Reduced Memory Requirement

“…8, four bar graphs describe computation flow of ACS operation and denote equations of critical path delay indicated in Eqs. (3), (7), (12) and (14). Type-L2 has the shortest critical path delay which is obtained by comparing the magnitude of six pre-compare metrics all together.…”

“…To increase the throughput of SISO decoders, there are several methods such as the increase of parallelism of decoder [1][2][3][4][5][6][7][8][9][10], the improvement of operating frequency [11], and the high radix architecture [12][13][14]. This paper is focused on high operating frequency of radix-4 ACS unit for the high-throughput of radix-4 SISO decoders.…”