A 691 Mbps 1.392mm&lt;sup&gt;2&lt;/sup&gt; configurable radix-16 turbo decoder ASIC for 3GPP-LTE and WiMAX systems in 65nm CMOS

Chen, Xubin; Chen, Yun; Li, Yi; Huang, Yuebin; Zeng, Xiaoyang

doi:10.1109/asscc.2013.6691006

Cited by 2 publications

(4 citation statements)

References 9 publications

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“…To verify the effectiveness of the proposed architecture, the case study is performed with the published parallel turbo decoders [3], [4]. Table II indicates the energy consumption of the state-of-the-art parallel turbo decoders when the proposed CRC-based early stopping unit is adopted [3], [4].…”

Section: Implementation Resultsmentioning

confidence: 99%

“…Table II indicates the energy consumption of the state-of-the-art parallel turbo decoders when the proposed CRC-based early stopping unit is adopted [3], [4]. When the early stopping unit is not applied to the parallel turbo decoder, the energy consumptions of the published decoders are 5.643 and 5.744 μJ in [3] and [4], respectively, where the iteration number is fixed to 5.5 and the code block size is 6144 bits. However, by applying the early stopping unit, the total energy consumption can be reduced as represented in E Stop .…”

Section: Implementation Resultsmentioning

confidence: 99%

“…The conventional CRC operation calculating the total summation of the weighted subblock can be described by (3). To distribute the CRC operation to each weighted subblock, the subblock and its position are separated by CRC distributive law in (5) based on the Galois field linear property [6].…”

Section: B Crc Based On Galois Field Operationmentioning

confidence: 99%

See 2 more Smart Citations

Distributed CRC Architecture for High-Radix Parallel Turbo Decoding in LTE-Advanced Systems

Kim

Choi

Byun

et al. 2015

IEEE Trans. Circuits Syst. II

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This brief presents two types of distributed cyclic redundancy check (CRC) architecture for a high-radix parallel turbo decoder in LTE/LTE-advanced communication systems. The conventional CRC architecture in the parallel turbo decoder requires both huge timing overhead and energy waste since the CRC of the message is calculated after completion of the soft-input soft-output (SISO) decoding process or concurrently with the next SISO decoding, even though the message is already confirmed for its integrity. The distributed CRC architecture proposed in this brief computes the CRC while the message is decoded separately, and it can provide the stopping signal to the decoder with negligible computing latency after completion of the SISO decoding process. The two proposed architectures are based on Galois field arithmetic and implemented in a 65-nm CMOS process where various block sizes, degrees of parallelism, and radix numbers of the high-radix SISO decoder are supported.Index Terms-Distributed cyclic redundancy check (CRC), early stopping criteria, Galois fields, parallel turbo decoder.

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Section: Implementation Resultsmentioning

confidence: 99%

Section: Implementation Resultsmentioning

confidence: 99%

See 1 more Smart Citation

Distributed CRC Architecture for High-Radix Parallel Turbo Decoding in LTE-Advanced Systems

Kim

Choi

Byun

et al. 2015

IEEE Trans. Circuits Syst. II

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“…In this section, we quantify the flexibility of each channel decoder by the number of supported combinations of block length K and coding rate R. Figure 11 characterises the flexibility, scaled average area-efficiency and energy-efficiency that is achieved by each turbo, LDPC and polar decoder ASIC considered. In the case of the turbo decoders, the number of information block lengths K supported is determined by the number of interleavers supported, which is 188 Average Scaled Energy Efficiency (bit/nJ) [45], [58], [63], [67]- [72] [65], [73]- [76] [52], [77], [78] [64], [79], [80] [51], [81]- [85] Inflexible Fl ex ib le Fig. 11: Area-efficiency (M bps/mm 2 ) versus the reconfiguration flexibility between state-of-the-art turbo, LDPC and inflexible polar decoder ASICs when scaled to 65 nm.…”

Section: Reconfiguration Flexibility Vs Area-and Energyefficiencymentioning

confidence: 99%

Survey of Turbo, LDPC, and Polar Decoder ASIC Implementations

Shao

Hailes

Wang

et al. 2019

IEEE Commun. Surv. Tutorials

106

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Channel coding may be viewed as the bestinformed and most potent component of cellular communication systems, which is used for correcting the transmission errors inflicted by noise, interference and fading. The powerful turbo code was selected to provide channel coding for Mobile Broad Band (MBB) data in the 3G UMTS and 4G LTE cellular systems. However, the 3GPP standardization group has recently debated whether it should be replaced by Low Density Parity Check (LDPC) or polar codes in 5G New Radio (NR), ultimately reaching the decision to adopt the LDPC code family for enhanced Mobile Broad Band (eMBB) data and polar codes for eMBB control. This paper summarises the factors that influenced this debate, with a particular focus on the Application Specific Integrated Circuit (ASIC) implementation of the decoders of these three codes. We show that the overall implementation complexity of turbo, LDPC and polar decoders depends on numerous other factors beyond their computational complexity. More specifically, we compare the throughput, error correction capability, flexibility, area efficiency and energy efficiency of ASIC implementations drawn from 110 papers and use the results for characterising the advantages and disadvantages of these three codes as well as for avoiding pitfalls and for providing design guidelines.

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A 691 Mbps 1.392mm<sup>2</sup> configurable radix-16 turbo decoder ASIC for 3GPP-LTE and WiMAX systems in 65nm CMOS

Cited by 2 publications

References 9 publications

Distributed CRC Architecture for High-Radix Parallel Turbo Decoding in LTE-Advanced Systems

Distributed CRC Architecture for High-Radix Parallel Turbo Decoding in LTE-Advanced Systems

Survey of Turbo, LDPC, and Polar Decoder ASIC Implementations

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