High speed FIR filter implementation using add and shift method

Mirzaei, Shahnam; Hosangadi, Anup; Kastner, Ryan

doi:10.1145/1117201.1117251

Cited by 9 publications

(12 citation statements)

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“…We selected a set of benchmark circuits including multipliers (m12x12, m16x16), FIR filters (fir3) [1], motion estimation for video coding (ME) [3], and some circuits where multi-operand addition was exposed via circuit transformations [12]; only the compressor tree and final adder are synthesized here. Fig.…”

Section: Resultsmentioning

confidence: 99%

“…One of the most important arithmetic operations in many DSP and video processing applications is multi-operand addition, i.e., the addition of k > 2 binary integers. Multi-input addition occurs in the context of FIR filters [1], correlation of 3G wireless base-station channel cards [2], motion estimation in video coding [3], and partial product summation in parallel multiplication [4,5,6,7,[8][9][10]11]. Verma and Ienne [12] developed a set of circuit transformations that can expose large compressor trees from disparate addition and multiplication operations.…”

Section: Introductionmentioning

confidence: 99%

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Improving synthesis of compressor trees on FPGAs via integer linear programming

Parandeh-Afshar

Brisk

Ienne

2008

Proceedings of the Conference on Design, Automation and Test in Europe

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Multi-input addition is an important operation for many DSP and video processing applications. On FPGAs, multi-input addition has traditionally been implemented using trees of carry-propagate adders. This approach has been used because the traditional lookup table (LUT) structure of FPGAs is not amenable to compressor trees, which are used to implement multi-input addition and parallel multiplication in ASIC technology. In prior work, we developed a greedy heuristic method to map compressor trees onto the general logic of an FPGA using a component called generalized parallel counter (GPC). Although this technique reduced the combinational delay of our circuits, when synthesized onto Altera Stratix-II FPGAs, by 27% on average; however, the area was increased by an average 11%. To further reduce the delay and limit the increase in area, we have developed a new solution to the mapping problem based on integer linear programming. This new approach reduced the delay of the compressor tree by 32% on average and reduced the area by 3% compared to an adder tree.

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Improving synthesis of compressor trees on FPGAs via integer linear programming

Parandeh-Afshar

Brisk

Ienne

2008

Proceedings of the Conference on Design, Automation and Test in Europe

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“…Multi-Operand addition occurs in a variety of signal processing applications, such as FIR filters [4]; Arithmetic transformations [5]; motion estimation [6] and correlators used in wireless communication [7]; In commercial FPGA device, multi-operand addition is realized on general logic resource, which is comprised of LUTs and carry chains [8,9,10], so the performance is limited.…”

Section: Introductionmentioning

confidence: 99%

Prototyping design of a flexible DSP block with pipeline structure for FPGA

Wang

Lai

2016

IEICE Electron. Express

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Embedded hard DSP block effectively improves FPGA performance for arithmetic circuits. This paper proposes a novel DSP architecture. By adopting a new Compressor Array, the proposed DSP can additionally supports multi-operand addition which current commercial devices do not support. This makes the DSP block more versatile to cover a wider range of applications. But supporting multi-operand addition will significantly increase routing congestion. To alleviate timing degeneration caused by the more congestion routing, we implement a pipelined design in the Compressor Array. The proposed DSP block is fabricated in 1P10M 65 nm bulk CMOS process, Test results show a 53.7% reduction in critical path delay compared to the Field Programmable Compressor Tree (FPCT).

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“…Compressor trees are circuits that perform multi-input addition and partial product reduction for parallel multiplication using carry-save arithmetic, which specifically avoids long chains of carry-propagate addition. Multi-input addition occurs in many multimedia and DSP applications such as motion estimation [3] and FIR [4] filters; moreover, systematic transformations can also optimize circuits by merging distinct carry-propagate adders with one another and with the partial product reduction trees of parallel multipliers, creating large multiinput adders [5]. Accelerating these multi-input adders can significantly improve the overall performance of the application.…”

Section: Introductionmentioning

confidence: 99%

Exploiting fast carry-chains of FPGAs for designing compressor trees

Parandeh-Afshar

Brisk

Ienne

2009

2009 International Conference on Field Programmable Logic and Applications

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Fast carry chains featuring dedicated adder circuitry is a distinctive feature of modern FPGAs. The carry chains bypass the general routing network and are embedded in the logic blocks of FPGAs for fast addition. Conventional intuition is that such carry chains can be used only for implementing carry-propagate addition; state-of-the-art FPGA synthesizers can only exploit the carry chains for these specific circuits. This paper demonstrates that the carry chains can be used to build compressor trees, i.e., multi-input addition circuits used for parallel accumulation and partial product reduction for parallel multipliers implemented in FPGA logic. The key to our technique is to program the lookup tables (LUTs) in the logic blocks to stop the propagation of carry bits along the carry chain at appropriate points. This approach improves the area of compressor trees significantly compared to previous methods that synthesized compressor trees solely on LUTs, without compromising the performance gain over trees built from ternary carry-propagate adders.

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High speed FIR filter implementation using add and shift method

Cited by 9 publications

References 0 publications

Improving synthesis of compressor trees on FPGAs via integer linear programming

Improving synthesis of compressor trees on FPGAs via integer linear programming

Prototyping design of a flexible DSP block with pipeline structure for FPGA

Exploiting fast carry-chains of FPGAs for designing compressor trees

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