Improving synthesis of compressor trees on FPGAs via integer linear programming

Abstract

Multi-input addition is an important operation for many DSP and video processing applications. On FPGAs, multi-input addition has traditionally been implemented using trees of carry-propagate adders. This approach has been used because the traditional lookup table (LUT) structure of FPGAs is not amenable to compressor trees, which are used to implement multi-input addition and parallel multiplication in ASIC technology. In prior work, we developed a greedy heuristic method to map compressor trees onto the general logic of an FPGA using a component called generalized parallel counter (GPC). Although this technique reduced the combinational delay of our circuits, when synthesized onto Altera Stratix-II FPGAs, by 27% on average; however, the area was increased by an average 11%. To further reduce the delay and limit the increase in area, we have developed a new solution to the mapping problem based on integer linear programming. This new approach reduced the delay of the compressor tree by 32% on average and reduced the area by 3% compared to an adder tree.

Power and delay aware synthesis of multi-operand adders targeting LUT-based FPGAs

“…The key idea of our approach is to formalize the problem based on not the compressor tree structures like [6], but the reduction process itself. Assume that y xx (i, j) is the number of GP C xx used at stage i for rank j, where xx is any element of the set {06, 05, 04, 03, 02, 15, 14, 13, 12, 23, 22}, and st is the number of stages, the objective is to minimize the following value:…”

“…RELATED WORK GPC-based compressor tree synthesis has been addressed firstly in [5], and several heuristics [5], [7] and an ILPbased approach [6] have been proposed. The objective of the heuristics are to minimize the maximum level of GPCs firstly and reduce the number of GPCs indirectly by using GPCs with larger reduction ratios greedily.…”

Implementation of large size multipliers using ternary adders and higher order compressors

“…In this Section, we describe the ternary adder and Generalized Parallel Counter (GPC) [4,5] and the methods of mapping onto logic blocks in FPGAs. At the next section, these structures will be used for the implementation of large size unsigned multiplication.…”

“…The Generalized Parallel Counter (GPC) introduced in [4,5] sums multiple input bits that may be located at different bit positions. Assume that the GPC has at most M input and N output bits.…”

“…This architecture will facilitate efficient mapping of the compressors. In this paper, we present an improved design approach for the implementation of large size multiplication using ternary adder and Generalized Parallel Counter [4,5] schemes.…”