Exploiting fast carry-chains of FPGAs for designing compressor trees

Abstract

Fast carry chains featuring dedicated adder circuitry is a distinctive feature of modern FPGAs. The carry chains bypass the general routing network and are embedded in the logic blocks of FPGAs for fast addition. Conventional intuition is that such carry chains can be used only for implementing carry-propagate addition; state-of-the-art FPGA synthesizers can only exploit the carry chains for these specific circuits. This paper demonstrates that the carry chains can be used to build compressor trees, i.e., multi-input addition circuits used for parallel accumulation and partial product reduction for parallel multipliers implemented in FPGA logic. The key to our technique is to program the lookup tables (LUTs) in the logic blocks to stop the propagation of carry bits along the carry chain at appropriate points. This approach improves the area of compressor trees significantly compared to previous methods that synthesized compressor trees solely on LUTs, without compromising the performance gain over trees built from ternary carry-propagate adders.

Synthesis of Floating-Point Addition Clusters on FPGAs Using Carry-Save Arithmetic

“…Trees of IEEE 2-input floating-point adders were non-competitive compared to Altera's floating-point datapath compiler [1,2] for more than two operands. Two implementations of our synthesis method are shown: one which builds the multi-operand adder as a tree of 3-input adders (with each ALM configured in Shared Arithmetic Mode), and one that implements it using a carry-save-based compressor tree [3]; the former achieves tigher area bounds, while the latter improves critical path delay.…”

“…It takes advantage of advances in FPGA synthesis for multi-operand additions using carry save arithmetic [3], and includes a new approach to computing the maximum value among a set of k unsigned integers. …”

“…The case where the result is zero is handled as a special case. Assume that the significand resulting from the second effective operation has the form 0.F 3 ; we must first count the number of leading zeroes in 0.F 3 Round: This final step accounts for the error incurred due to the bits that were shifted right during significand alignment. A value of 1 is added to the significand based on the rounding mode specified and the values of the guard, round, and sticky bits, G, R, and T, as discussed earlier; this may once again cause overflow, such that the result has the form 10.F; this case is handled identically to normalization for effective addition: the significand is shifted right by one, normalizing it, and the exponent is incremented.…”

“…This paper presents a new approach to synthesize floatingpoint addition clusters. All significands are denormalized with respect to the largest exponent among all input operands, and a compressor tree [3] sums the denormalized significands; the result is normalized, rounded, and packed into a floating-point number along with the resulting exponent and sign bit. Compared to Altera's compiler [1,2] our approach improves critical path delay up to 20% and area up to 29%.…”

Reducing the pressure on routing resources of FPGAs with generic logic chains

“…In a previous contribution [21], we mapped generalized parallel counters, also used for multi-operand addition, onto the carry chains used by Altera's Stratix III series FPGAs, which are still in use today. This approach target a limited set of logic functions (multi-operand addition) and cannot map general logic functions onto carry chains.…”