High-speed and low-power multipliers using the Baugh-Wooley algorithm and HPM reduction tree

Själander, Magnus; Larsson-Edefors, Per

doi:10.1109/icecs.2008.4674784

Cited by 39 publications

(19 citation statements)

References 10 publications

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“…Although other (possibly more efficient) techniques exist for signed multiplication [Parhami 2000;Sjalander and Larsson-Edefors 2008], Booth has the advantage that it is widely adopted and particularly well supported in the Synopsys design flow. In our prototype (Section 7), Synopsys DesignWare components [Synopsys 2011] were used to implement parts of the core functionality.…”

Section: Exponent Datapath and Alignment Shifter Equationsmentioning

confidence: 99%

Sabrewing

Bruintjes

Walters

Gerez

et al. 2012

ACM Trans. Archit. Code Optim.

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In spite of the fact that floating-point arithmetic is costly in terms of silicon area, the joint design of hardware for floating-point and integer arithmetic is seldom considered. While components like multipliers and adders can potentially be shared, floating-point and integer units in contemporary processors are practically disjoint. This work presents a new architecture which tightly integrates floating-point and integer arithmetic in a single datapath. It is mainly intended for use in low-power embedded digital signal processors and therefore the following design constraints were important: limited use of pipelining for the convenience of the compiler; maintaining compatibility with existing technology; minimal area and power consumption for applicability in embedded systems. The architecture is tailored to digital signal processing by combining floating-point fused multiply-add and integer multiply-accumulate. It could be deployed in a multi-core system-on-chip designed to support applications with and without dominance of floating-point calculations.The VHDL structural description of this architecture is available for download under BSD license. Besides being configurable at design time, it has been thoroughly checked for IEEE-754 compliance by means of a floating-point test suite originating from the IBM Research Labs. A proof-of-concept has also been implemented using STMicroelectronics 65nm technology. This prototype supports 32-bit signed two's complement integers and 41-bit (8-bit exponent and 32-bit significand) floating-point numbers. Our evaluations show that over 67% energy and 19% area can be saved compared to a reference design in which floating-point and integer arithmetic are implemented separately. The area overhead caused by combining floating-point and integer is less than 5%.Implemented in ST's general-purpose CMOS technology, the design can operate at a frequency of 1.35GHz, while 667MHz can be achieved in low-power CMOS. Considering that the entire datapath is partitioned in just three pipeline stages, and the fact that the design is intended for use in the low-power domain, these frequencies are adequate. They are in fact competitive with current technology low-power floating-point units. Post-layout estimates indicate that the required area of a low-power implementation can be as small as 0.04mm 2 . Power consumption is on the order of several milliwatts. Strengthened by the fact that clock gating could reduce power consumption even further, we think that a shared floating-point and integer architecture is a good choice for signal processing in low-power embedded systems.

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Section: Exponent Datapath and Alignment Shifter Equationsmentioning

confidence: 99%

Sabrewing

Bruintjes

Walters

Gerez

et al. 2012

ACM Trans. Archit. Code Optim.

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“…The partial products are generated more efficiently using lower number of transistors. The proposed two multipliers offer significant improved performance, in terms of speed and power dissipation, than standard array multipliers [9].…”

Section: Iirelated Workmentioning

confidence: 99%

Design and Implementation of Folded FIR Filter Structures using High Speed Multipliers

Kumar¹,

Kavitha²,

dhini³

2014

IJAREEIE

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ABSTRACT:Modern DSP systems are often well suited to VLSI implementation. Indeed, they are often technically feasible or economically viable only if implemented using VLSI technologies.. The paper is focused on the design of an efficient VLSI architecture for FIR filters which aims at reducing the power consumption and also to reduce the hardware complexity. In the existing method, design of folded FIR filter based on conventional multiplier is presented. It does not allow the internal pipelining delays to be exploited. It leads to significant increase in hardware as well as considerable increase in power consumption. It leads to less throughput and increases hardware complexity. In the proposed method, design of folded finite-impulse response (FIR) filters based on pipelined carry-save multiplier is presented . The design is considered at the bit-level and the internal delays of the pipelined multiplier array are fully exploited in order to reduce hardware complexity. Partially folded architectures are also proposed which are implemented by cascading a number of folded FIR filters. The proposed schemes are compared as to the aspect of hardware complexity with a straightforward implementation of a folded FIR filter based on the conventional multipier . The comparison reveals that the proposed schemes may require 20%-30% less hardware. Due to the lesser carry propagation, the proposed method can achieve low power consumption and higher computational speed strategy.

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“…Various structures FPGA implementable high speed filters are discussed in literature. The An IIR filter is a recursive filter where the current output proposed design in this paper is an attempt to optimize the depends on previous outputs [5].The condensed form of the system speed with minimal cost of hardware and software. This extremely high speed comes due to above-stated advanced signal processing techniques.…”

Section: Introductionmentioning

confidence: 99%

survey paper on high speed IIR filter using pipelined

2017

IJMTER

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Abstract-Field-Programmable-Gate-Array (FPGA) based design and implementation of extremely high speed realization of Infinite Impulse Response (IIR) filter. The IIR Filters are being designed using HDL languages since speed is among the chief interest in this era; the main objective is to enhance the speed of the system. In the whole system if the speed of the individual block is enhanced the overall speed of the system is enhanced digital computer arithmetic is an aspect of logic design with the objective of developing appropriate algorithms in order to attain an effective utilization of the available hardware. To generalize its FPGA based design for specific speed up factor, a new efficient simpler approach utilizing Pascal's Triangle is proposed to calculate the multiplier coefficients of feed-forward and feedback sections of extremely high speed IIR Filter. Since ultimately, speed, power and chip area are the most often used measures of the efficiency of an algorithm, there has a strong link between the algorithms and technology applied for its implementation. Here it is done by applying the technique pipelining. The comparative analysis of pipelined IIR filters is performed by using different FPGA's. The results reveal that the implemented filters turn in a consistent quality of output.

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High-speed and low-power multipliers using the Baugh-Wooley algorithm and HPM reduction tree

Cited by 39 publications

References 10 publications

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Design and Implementation of Folded FIR Filter Structures using High Speed Multipliers

survey paper on high speed IIR filter using pipelined

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