High-speed, accurate analogue CMOS rank filter

Fikos, G.; Vlassis, S.; Siskos, S.

doi:10.1049/el:20000428

Cited by 17 publications

(11 citation statements)

References 3 publications

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“…In (3) the transconductance parameter mismatch is omitted due to its relatively low impact [21] on the total input offset voltage. The contribution of the load to the offset voltage, referred to the input, is determined as a current mismatches (DI DS ) 5,6 and (DI DS ) 3,4 , between two pairs M5-M6 and M3-M4, divided by the voltage-current gain g m1,2 of the differential pair, which results in…”

Section: Corner Errorsmentioning

confidence: 99%

“…where (DV T ) 5,6 and (DV T ) 3,4 represent the mismatches of the threshold voltages between M5-M6 and M3-M4. The threshold voltage mismatch can be expressed in terms of the standard deviation r by means of the Pelgrom's formula [23,21] where A V T is a parameter specific for a selected technology.…”

Section: Corner Errorsmentioning

confidence: 99%

“…For this reason, the median filtering greatly facilitates further image processing such as the edge detection or the segmentation. In integrated circuits, the median filters are implemented using both analog [2][3][4][5][6][7][8][9][10][11][12][13][14][15][16] and digital [17][18][19][20] techniques, depending on the design requirements. Typically, the greatest reduction of consumed power and required chip area are achievable using analog median filters, because they do not require analog to digital converters (ADC) for conversion of video signals generated by photo sensors.…”

Section: Introductionmentioning

confidence: 99%

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A nine-input 1.25 mW, 34 ns CMOS analog median filter for image processing in real time

Jendernalik

Blakiewicz

Jakusz

et al. 2013

Analog Integr Circ Sig Process

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In this paper an analog voltage-mode median filter, which operates on a 3 9 3 kernel is presented. The filter is implemented in a 0.35 lm CMOS technology. The proposed solution is based on voltage comparators and a bubble sort configuration. As a result, a fast (34 ns) time response with low power consumption (1.25 mW for 3.3 V) is achieved. The key advantage of the configuration is relatively high accuracy of signal processing, which allows the calculation of the median of signals with the difference in amplitude as small as 10 mV. This feature allows the application of the filter to vision systems with up to 7 bit equivalent resolution. The analytical and statistical analysis of the filter resolution, and analysis of its speed limitations are presented and compared to measurement results. Based on the achieved results, a set of guidelines for the filter design and optimisation is presented.

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Section: Corner Errorsmentioning

confidence: 99%

Section: Corner Errorsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A nine-input 1.25 mW, 34 ns CMOS analog median filter for image processing in real time

Jendernalik

Blakiewicz

Jakusz

et al. 2013

Analog Integr Circ Sig Process

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“…The worst case of the total propagation delay can be calculated using (4), (5a), (6), and (3). Assuming that: (W/L) 1,2 = 10 µm/1 µm, (W/L) 3−6 = 2 µm/1 µm, I bias = 10 µA, and n = 2, the following results were obtained: ∆V A = 0.34 V, SR A = 61.7 V/µs, and SR + B = 2270 V/µs.…”

Section: Cmos Implementation Of An Analogue Median Filter For Image Pmentioning

confidence: 99%

“…Due to that advantageous properties the median filtering greatly facilitates further image processing such as edge detection or segmentation. Two kinds of techniques are used in integrated circuits to implement the median filters, analogue [2][3][4][5][6][7][8][9][10][11][12][13][14][15] and digital [16][17][18][19], depending on the design requirements. Typically, the analogue median filters allow a greater reduction in power consumption, because they do not require analogue to digital conversion (ADC) of the video signals generated by the photo sensors.…”

Section: Introductionmentioning

confidence: 99%

CMOS implementation of an analogue median filter for image processing in real time

Jendernalik¹,

Jakusz²,

Blakiewicz³

et al. 2013

Bulletin of the Polish Academy of Sciences: Technical Sciences

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Abstract. An analogue median filter, realised in a 0.35 µm CMOS technology, is presented in this paper. The key advantages of the filter are: high speed of image processing (50 frames per second), low-power operation (below 1.25 mW under 3.3 V supply) and relatively high accuracy of signal processing. The presented filter is a part of an integrated circuit for image processing (a vision chip), containing: a photo-sensor matrix, a set of analogue pre-processors, and interface circuits. The analysis of the main parameters of the considered median filter is presented. The discussion of important limitations in the operation of the filter due to the restrictions imposed by CMOS technology is also presented.

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