A nine-input 1.25 mW, 34 ns CMOS analog median filter for image processing in real time

Jendernalik, W.; Blakiewicz, Grzegorz; Jakusz, J.; Szczepański, S.

doi:10.1007/s10470-013-0103-1

Cited by 8 publications

(3 citation statements)

References 23 publications

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“…Hardware implementations of median filters, not specifically designed for processing EEG signals, have been previously reported in the literature and proven to be power hungry. A 3 input median filter has been proposed in [19] consuming 14 mW and the work of [20] reports a 9 input median circuit consuming 1.25 mW. Since in (2), the median operation is performed on the input signal and its time-shifted copies, the required delay elements (60 in the case of (2)) would only add to the hardware implementation complexity and power consumption.…”

Section: Seizure Selectionmentioning

confidence: 99%

A Seizure-Based Power Reduction SoC for Wearable EEG in Epilepsy

et al. 2019

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Epilepsy is one of the most common serious brain disorders affecting 1% of the world population. Epileptic seizure events are caused by abnormal excessive neuronal activity in the brain, which may be associated with behavioural changes that severely affect the patients' quality of life. These events are manifested as abnormal activity in electroencephalography (EEG) recordings of individuals with epilepsy. This paper presents the on-chip implementation of an algorithm that, operating on the principle of data selection applied to seizures, would be able to reduce the power consumption of EEG devices, and consequently their size, thereby significantly increasing their usability. In order to reduce the power consumed by the on-chip implementation of the algorithm, mathematical approximations have been carried out to allow for an analog implementation, resulting in the power consumed by the system to be negligible in comparison to other blocks in an EEG device. The system has been fabricated in a 0.18 µm CMOS process, consumes 1.14 µW from a 1.25 V supply and achieves a sensitivity of 98.5% while only selecting 52.5% of the EEG data for transmission.

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Section: Seizure Selectionmentioning

confidence: 99%

A Seizure-Based Power Reduction SoC for Wearable EEG in Epilepsy

et al. 2019

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“…Assuming that ∆V TH is a small-signal variation and using the results of [15] and [17], the input-referred offset voltage of the comparator in Fig. 3 can be expressed as…”

Section: Comparator I (Complex Structure)mentioning

confidence: 99%

On analog comparators for CMOS digital pixel applications. A comparative study

Jendernalik

2016

Bulletin of the Polish Academy of Sciences Technical Sciences

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Abstract. Voltage comparator is the only -apart from the light-to-voltage converter -analog component in the digital CMOS pixel. In this work, the influence of the analog comparator nonidealities on the performance of the digital pixel has been investigated. In particular, two versions of the digital pixel have been designed in 0.35 µm CMOS technology, each using a different type of analog comparator. The properties of both versions have been compared. The first pixel utilizes a differential comparator with the increased size and improved electrical performance. The second structure is based on a very simple non-differential comparator with a reduced size and degraded performance. Theoretical analysis of the comparator nonideality effect on the quality of the image obtained from the digital pixel matrix as well as simulation results are provided.Key words: CMOS image sensor, CMOS digital pixel, analog comparator, fixed pattern noise (FPN). On analog comparators for CMOS digital pixel applications.A comparative study W. JENDERNALIK* Faculty of Electronics Telecommunications and Informatics, Gdańsk University of Technology, 11/12 Narutowicza St., 80-952 Gdańsk, Poland pixels containing a photosensor and a complete A/D converter are larger than 20 µm × 20 µm. This results in degradation of the fill factor, increase of the matrix area, and the increase of the integrated image sensor price. For this reason, development of A/D converter solutions that can be implemented on a small pixel while maintaining sufficiently large bit resolution and high conversion quality becomes of primary importance. One of the most important components of the A/D converter is a CMOS analog voltage comparator. Such a comparator usually consists of a conventional MOS differential pair with a current mirror as an active load, an amplifier stage implemented as a common-source configuration, as well as one or two CMOS inverters which work as an additional amplification stage. The comparator footprint may contribute to as much as 20 to 30 percent of the entire pixel area [7]. In order to reduce the comparator size, one needs to reduce the sizes of its transistors, which leads to degrading the electrical performance of the circuit. Smaller transistor size means larger technological spread of their parameters and the increased offset voltage of the comparator. Moreover, the 1/f noise level is also increased.In this work, we investigate a possibility of applying -in a digital pixel -a simple non-differential analog comparator consisting of four CMOS transistors. Such a comparator is characterized by worse electrical performance compared to a conventional differential comparator; however, it features a considerably smaller footprint. In order to compare the influence of the analog comparator performance on the image quality, two versions of a digital pixel realized in 0.35 µm CMOS technology have been designed. The pixels are only different with respect to the analog comparator. Simulation studies have been performed for the two matrices of the siz...

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“…Dobierając wymiary tranzystorów kierowano się kompromisem pomiędzy powierzchnią topografii a parametrami elektrycznymi komparatora. Na przykład rozmiary tranzystorów stopnia różnicowego dobrano tak [9], aby uzyskać wejściowe napięcie niezrównoważenia poniżej 1 LSB  9 mV. Wymiary tranzystorów są następujące: (W/L) 1,2 = 7µm/0,7µm, (W/L) 3,4 = 1,4µm/0,7µm, (W/L) 5 = 2,5µm/0,35µm, (W/L) 6 = 2,5µm/0,5µm, (W/L) 7-11 = 0,4µm/0,35µm.…”

Section: Rys 4 Topografia Komparatora Z Rysunkuunclassified

Niskomocowy komparator z zatrzaskiem przeznaczony do cyfrowego przetwornika obrazu CMOS

Jakusz

2015

ELECTROTECHNICAL REVIEW

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Streszczenie. W artykule zaproponowano realizację analogowego niskomocowego komparatora z zatrzaskiem przeznaczonego do cyfrowego piksela CMOS. Komparator zaprojektowano w technologii 0,35 µm CMOS. Układ zoptymalizowano pod kątem obniżenia poboru mocy ze źródła zasilającego i powierzchni topografii. W projekcie zastosowano techniki redukcji poboru mocy statycznej i dynamicznej. Komparator przebadano symulacyjnie w układzie cyfrowego piksela z przetwornikiem A/C typu single-slope. Układ zasilany napięciem 3,3 V pobiera moc 1,8 µW przy założeniu 100 tysięcy cykli konwersji A/C na sekundę i zajmuje powierzchnię 220 µm 2 .

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A nine-input 1.25 mW, 34 ns CMOS analog median filter for image processing in real time

Cited by 8 publications

References 23 publications

A Seizure-Based Power Reduction SoC for Wearable EEG in Epilepsy

A Seizure-Based Power Reduction SoC for Wearable EEG in Epilepsy

On analog comparators for CMOS digital pixel applications. A comparative study

Niskomocowy komparator z zatrzaskiem przeznaczony do cyfrowego przetwornika obrazu CMOS

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