High resolution inspection with wafer plane die: database defect detection

Hess, Carl; Wihl, M.; Shi, Rui-Fang; Xiong, Yalin; Pang, Song

doi:10.1117/12.801867

Cited by 3 publications

(2 citation statements)

References 7 publications

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“…[84][85][86][87][88][89][130][131][132][133][134] KLA has introduced WPI/API to examine the impact on the wafer as a way to filter defects on mask. [135][136][137] Brion Technologies and NuFlare developed off-line lithography simulation software for the NuFlare mask inspection system. 90,91 Luminescent Technologies, after it sold its ILT business to Synopsys, also developed its LAIPH™ Litho Plane Reviewer system targeting for ILT mask defect dispositioning.…”

Section: Curvilinear Mask Inspectionmentioning

confidence: 99%

Inverse lithography technology: 30 years from concept to practical, full-chip reality

Pang

2021

J. Micro/Nanopattern. Mats. Metro.

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In lithography, optical proximity and process bias/effects need to be corrected to achieve the best wafer print. Efforts to correct for these effects started with a simple bias, adding a hammer head in line-ends to prevent line-end shortening. This first-generation correction was called rule-based optical proximity correction (OPC). Then, as chip feature sizes continued to shrink, OPC became more complicated and evolved to a model-based approach. Some extra patterns were added to masks, to improve the wafer process window, a measure of resilience to manufacturing variation. Around this time, the concept of inverse lithography technology (ILT), a mathematically rigorous inverse approach that determines the mask shapes that will produce the desired on-wafer results, was introduced. ILT has been explored and developed over the last three decades as the next generation of OPC, promising a solution to several challenges of advanced-node lithography, whether optical or extreme ultraviolet (EUV). Today, both OPC and ILT are part of an arsenal of lithography technologies called resolution enhancement technologies. Since OPC and ILT both involve computation, they are also considered as part of computational lithography. We explore the background and history of ILT and detail the significant milestones that have taken full-chip ILT from an academic concept to a practical production reality.

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Section: Curvilinear Mask Inspectionmentioning

confidence: 99%

Inverse lithography technology: 30 years from concept to practical, full-chip reality

Pang

2021

J. Micro/Nanopattern. Mats. Metro.

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“…Although alternative solutions have been actively explored, [1,2] currently, hardware based, AIMS (Aerial Image Measurement System) like equipment is still the tool of choice for mask defect printability check. However, when moving into sub-65nm technology nodes, a new system is needed to match advanced scanners and the existing systems do not have the resolution to resolve some of the features in sub-65nm masks.…”

Section: Introductionmentioning

confidence: 99%

Simulation based mask defect repair verification and disposition

et al. 2009

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As the industry moves towards sub-65nm technology nodes, the mask inspection, with increased sensitivity and shrinking critical defect size, catches more and more nuisance and false defects. Increased defect counts pose great challenges in the post inspection defect classification and disposition: which defect is real defect, and among the real defects, which defect should be repaired and how to verify the post-repair defects.In this paper, we address the challenges in mask defect verification and disposition, in particular, in post repair defect verification by an efficient methodology, using SEM mask defect images, and optical inspection mask defects images (only for verification of phase and transmission related defects).We will demonstrate the flow using programmed mask defects in sub-65nm technology node design. In total 20 types of defects were designed including defects found in typical real circuit environments with 30 different sizes designed for each type. The SEM image was taken for each programmed defect after the test mask was made. Selected defects were repaired and SEM images from the test mask were taken again. Wafers were printed with the test mask before and after repair as defect printability references.A software tool SMDD-Simulation based Mask Defect Disposition-has been used in this study. The software is used to extract edges from the mask SEM images and convert them into polygons to save in GDSII format. Then, the converted polygons from the SEM images were filled with the correct tone to form mask patterns and were merged back into the original GDSII design file. This merge is for the purpose of contour simulation-since normally the SEM images cover only small area (~1 μm) and accurate simulation requires including larger area of optical proximity effect. With lithography process model, the resist contour of area of interest (AOI-the area surrounding a mask defect) can be simulated. If such complicated model is not available, a simple optical model can be used to get simulated aerial image intensity in the AOI. With built-in contour analysis functions, the SMDD software can easily compare the contour (or intensity) differences between defect pattern and normal pattern. With user provided judging criteria, this software can be easily disposition the defect based on contour comparison. In addition, process sensitivity properties, like MEEF and NILS, can be readily obtained in the AOI with a lithography model, which will make mask defect disposition criteria more intelligent.

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Your worst nightmare: inspection of aggressive OPC on 14nm masks with emphasis on defect sensitivity and wafer defect print predictability

Badger¹,

Hibbs²,

Rankin³

et al. 2013

SPIE Proceedings

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To prevent catastrophic failures during wafer manufacturing, mask manufacturers employ sophisticated reticle inspection systems to examine every image on every reticle to identify defects. These advanced systems inspect at resolutions typically 3x higher at the reticle-plane than advanced wafer scanners; thus enabling them to detect the small defects necessary to ensure reticle quality.The most thorough inspection is done using a reticle-to-database comparison that ensures the reticle pattern matches the design pattern. For high defect sensitivity, the database must be carefully modeled to exactly match the reticle pattern. Further, sub-resolution OPC shapes are often at the limit of the mask manufacturing process, which adds subtle variations on such shapes across the reticle. These modeling errors and process variations can cause high numbers of unwanted detections, thereby limiting inspection system defect detection sensitivity. [1] OPC designs are expected to become more aggressive for future generations and may stress the performance of current reticle inspection systems. To systematically assess the capability of various inspection approaches and identify needed areas for improvement, a new "Nightmare" test reticle has been designed by IBM. The test reticle contains various sizes and shapes of sub-resolution features that might appear on reticle generations from today's 22nm to future 7nm. It also contains programmed defects to assess defect detection capability of current and future generation inspection systems. This paper will discuss the design of the "Nightmare" test reticle, and the inspection results of the current generation reticle inspection methods with emphasis on both inspectability and defect sensitivity. The subresolution features will be ranked according to importance for advanced OPC design. The reticle will also be evaluated using wafer print simulation so lithographic impact of features and defects can be measured and compared against inspection approaches and results.

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High resolution inspection with wafer plane die: database defect detection

Cited by 3 publications

References 7 publications

Inverse lithography technology: 30 years from concept to practical, full-chip reality

Inverse lithography technology: 30 years from concept to practical, full-chip reality

Simulation based mask defect repair verification and disposition

Your worst nightmare: inspection of aggressive OPC on 14nm masks with emphasis on defect sensitivity and wafer defect print predictability

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