High Resolution Digital Duty Cycle Modulation Schemes for Voltage Regulators

Dynamic DC ramp shift digital control technique for improved transient response

“…System requirements for minimum output voltage ripple ∆ and desired output voltage decide the resolution of the ADC. [20].…”

High Resolution FPGA DPWM Based on Variable Clock Phase Shifting

“…The second group of studies tries to increase the effective duty cycle resolution changing the pattern used in the generation of the output signal. Digital dither [1], [13], sigma-delta [7], [12], [17], and slightly-changing frequency [18] are three good examples of this group. The present study is part of the first group, proposing a new architecture for reducing the minimum time step.…”

ASIC and FPGA based DPWM architectures for single-phase and single-output DC-DC converter: a review

“…The architectures can be easily implemented either on ASIC or FPGA. However, the high switching frequency and high DPWM resolution may result in impractically large clock frequency requirement and thus large power consumption [53,63], which turns out to be the disadvantage.…”

“…This eliminates any mismatched delay in the path of delay cell output to the reset terminal of the flip-flop. These architectures use clock frequency as a switching frequency unlike in that used in counter based architectures, this helps to decrease the power consumption at the expense of large area due to area consuming multiplexer [3,53,55,63]. The size of the multiplexer grows exponentially with the increase in the resolution bits ( ).…”

“…The delay through the delay cell is the function of supply voltage (V ). This technique uses switching frequency as clock frequency; decreasing the power consumption at the expense of large chip size [5,6,63].…”