High reliability Cu interconnection utilizing a low contamination CoWP capping layer

Abstract

Copper (Cu) damascene interconnects with a cobalt tungsten phosphorus (CoWP) capping layer were developed using an alkaline-metal-free electroless plating process .without palladium (Pd) catalyst activation. The wafer contamination level after processing is consistent with requirements for present LSI fabrication lines. Within wafer CoWP deposition uniformity is high and interconnects wire resistance increases by less than 5% after deposition. Electromigration (EM) testing shows no failures after two thousand hours and stress induced voiding (SIV) testing shows no failures after three thousand hours. This EM result is a 2 order of magnitude improvement over a non CoWP process.

Copper Metal for Semiconductor Interconnects

“…It is noted that the maximum annealing temperature must be limited after dielectric capping layer deposition because high-temperature annealing after dielectric capping layer deposition can lead to high rates of stress-induced void formation due to either confined grain growth or due to increased stress in the Cu line [122,132]. Additionally, the use of metal capping layers [133] and/or Cu alloying lines [106,107], which are used to improve EM has also shown to reduce the failure rate of stress-induced void.…”

Process Technology for Copper Interconnects

“…Because the kinetics of void formation are controlled by interface and grainboundary diffusion [160], the rate of void growth can be reduced by using metal capping layers [161] or by alloying the Cu [135,136], similar to methods used to improve electromigration lifetime (Figure 8.21). As with electromigration, it is important to form a strongly adhering interface between the Cu and the capping layer in order to minimize vacancy diffusion along this fast-diffusion path.…”

Advances in multilayer graphene processes for metallization and high-frequency devices

“…Although Co caps were selectively formed by electroless plating of cobalt tungsten phosphide (CoWP) in the early stage, selective Co-CVD has been widely used for cap formation for mass production, and its application has been extended to Co liners for Cu filling by electroplating as one of the standard processes for Cu damascene interconnects. 6,7) In 2017, 20 years after the introduction of Cu, Co was introduced to replace Cu at the narrowest interconnect width. 8) It is considered that the introduction of the Co-cap process and Co-CVD equipment in mass production leads to the replacement of Cu with Co, since the introduction of new materials or processes is a difficult challenge in LSI manufacturing in general.…”