High Rate Deposition of Microcrystalline Silicon Using Conventional Plasma-Enhanced Chemical Vapor Deposition

Guo, Li Xin; Kondo, Michio; Fukawa, Makoto; Saitoh, K.; Matsuda, Akihisa

doi:10.1143/jjap.37.l1116

Cited by 234 publications

(95 citation statements)

References 11 publications

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“…As a possible solution for high-growth conditions of c-Si:H without damage to the surface layer, the highpressure depletion method was proposed. 3,11 In this approach, the application of a high discharge power is used to decompose most of the silane in initial reactions of the type SiH 4 → SiH x + ͑4−x͒H. Under the silane-depletion condition, the reaction…”

Section: A Structure Adjustment For Opm C-si:h Materialsmentioning

confidence: 99%

“…Other effective methods to reduce ion energies while maintaining high deposition rates are ͑i͒ very high frequency ͑VHF͒ excitation of the discharge, where lower peak-to-peak voltages for a given discharge power result in lower maximum-ion energies, [5][6][7][8][9] and ͑ii͒ high working pressure ͑p depo ͒ with an increased discharge power, where ion energies are reduced by multiple collisions in the plasma sheath. [10][11][12] Recently, also combinations of VHF-PECVD and high working pressure have been investigated. 3,[13][14][15][16][17] In the present paper we report on further studies of such a combination of VHF-PECVD at 94.7 MHz at high working pressures of 2-4 hPa for the growth of c-Si:H at high deposition rates.…”

Section: Introductionmentioning

confidence: 99%

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Microcrystalline silicon solar cells deposited at high rates

Mai

Klein

Carius

et al. 2005

Journal of Applied Physics

182

123

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Hydrogenated microcrystalline silicon ͑ c-Si:H͒ thin-film solar cells were prepared at high rates by very high frequency plasma-enhanced chemical vapor deposition under high working pressure. The influence of deposition parameters on the deposition rate ͑R D ͒ and the solar cell performance were comprehensively studied in this paper, as well as the structural, optical, and electrical properties of the resulting solar cells. Reactor-geometry adjustment was done to achieve a stable and homogeneous discharge under high pressure. Optimum solar cells are always found close to the transition from microcrystalline to amorphous growth, with a crystallinity of about 60%. At constant silane concentration, an increase in the discharge power did hardly increase the deposition rate, but did increase the crystallinity of the solar cells. This results in a shift of the c-Si:H/a-Si:H transition to higher silane concentration, and therefore leads to a higher R D for the optimum cells. On the other hand, an increase in the total flow rate at constant silane concentration did lead to a higher R D , but lower crystallinity. With this shift of the c-Si:H/a-Si:H transition at higher flow rates, the R D for the optimum cells decreased. A remarkable structure development along the growth axis was found in the solar cells deposited at high rates by a "depth profile" method, but this does not cause a deterioration of the solar cell performance apart from a poorer blue-light response. As a result, a c-Si:H single-junction p-i-n solar cell with a high efficiency of 9.8% was deposited at a R D of 1.1 nm/s.

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Section: A Structure Adjustment For Opm C-si:h Materialsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Microcrystalline silicon solar cells deposited at high rates

Mai

Klein

Carius

et al. 2005

Journal of Applied Physics

182

123

View full text Add to dashboard Cite

show abstract

“…The microcrystalline material was grown in the high pressure and high power regime, which facilitates the deposition at high deposition rates. 9,10 The deposition pressure of the i layer was 1330 Pa and the power density was 0.3 W / cm 2 . For these parameters a deposition rate of 0.3 nm/ s was achieved.…”

mentioning

confidence: 99%

Influence of contact effect on the performance of microcrystalline silicon thin-film transistors

Chan

Bunte

Stiebig

et al. 2006

Applied Physics Letters

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Microcrystalline silicon thin-film transistors were prepared by plasma-enhanced chemical vapor deposition at substrate temperatures below 200°C. The transistors exhibit electron mobilities of 38cm2∕Vs, threshold voltages in the range of 2V, and subthreshold slopes of 0.3V∕decade. Despite the realization of transistors with high carrier mobility, contact effects limit the performance of the transistors. The influence of the drain and source contacts on device parameters including the mobility, the threshold voltage, and the subthreshold slope will be discussed in detail.

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“…The microcrystalline material was grown in the high pressure and high power regime, which facilitates the deposition of microcrystalline films at high deposition rates. 5,6 The fabrication of c-Si: H by PECVD is characterized by the formation of a nucleation layer on the substrate. The electronic properties in this region of the film are inferior in comparison to the bulk properties of the c-Si: H and depend on the deposition conditions used.…”

Section: Introductionmentioning

confidence: 99%

Influence of low temperature thermal annealing on the performance of microcrystalline silicon thin-film transistors

Chan

Bunte

Stiebig

et al. 2007

Journal of Applied Physics

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Top-gate staggered microcrystalline silicon thin-film transistors (μc-Si:H TFTs) were prepared by plasma enhanced chemical vapor deposition at temperatures below 200°C. The μc-Si:H TFTs exhibit high effective electron mobilities (device mobilities) of up to 35cm2∕Vs for long channel devices. Due to the high carrier mobility μc-Si:H TFTs are promising devices for large area electronics such as organic light-emitting diode displays or radio frequency identification devices. The fabrication process of the μc-Si:H TFTs is similar to the fabrication process of amorphous silicon thin-film transistors, which facilitates an easy transfer of the technology to industry. In this paper, the influence of postfabrication low temperature thermal annealing (150°C) on the device properties of top-gate staggered μc-Si:H TFTs is investigated. Low temperature thermal annealing reduces the device threshold voltage and subthreshold slope. Furthermore, the annealing step results in an increase of the effective mobility for long channel transistors, whereas the effective mobility for short channel transistors is reduced. The influence of the postfabrication low temperature thermal annealing on the device performances will be discussed in detail.

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High Rate Deposition of Microcrystalline Silicon Using Conventional Plasma-Enhanced Chemical Vapor Deposition

Cited by 234 publications

References 11 publications

Microcrystalline silicon solar cells deposited at high rates

Microcrystalline silicon solar cells deposited at high rates

Influence of contact effect on the performance of microcrystalline silicon thin-film transistors

Influence of low temperature thermal annealing on the performance of microcrystalline silicon thin-film transistors

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