Influence of low temperature thermal annealing on the performance of microcrystalline silicon thin-film transistors

Abstract

Top-gate staggered microcrystalline silicon thin-film transistors (μc-Si:H TFTs) were prepared by plasma enhanced chemical vapor deposition at temperatures below 200°C. The μc-Si:H TFTs exhibit high effective electron mobilities (device mobilities) of up to 35cm2∕Vs for long channel devices. Due to the high carrier mobility μc-Si:H TFTs are promising devices for large area electronics such as organic light-emitting diode displays or radio frequency identification devices. The fabrication process of the μc-Si:H TFTs is similar to the fabrication process of amorphous silicon thin-film transistors, which facilitates an easy transfer of the technology to industry. In this paper, the influence of postfabrication low temperature thermal annealing (150°C) on the device properties of top-gate staggered μc-Si:H TFTs is investigated. Low temperature thermal annealing reduces the device threshold voltage and subthreshold slope. Furthermore, the annealing step results in an increase of the effective mobility for long channel transistors, whereas the effective mobility for short channel transistors is reduced. The influence of the postfabrication low temperature thermal annealing on the device performances will be discussed in detail.

Thin-film inverters based on high mobility microcrystalline silicon thin-film transistors

“…Prior to electrical measurements, all devices were annealed at 150°C for 30 min under ambient conditions. A detailed discussion of the influence of thermal annealing on the TFT characteristics is reported elsewhere [23].…”

Large area uniformity of plasma grown hydrogenated nanocrystalline silicon and its application in TFTs

“…Aluminum was evaporated above the n + nc-Si:H layer and then patterned to obtain the source (S) and drain (D) contacts. After performing post-deposition annealing at 423 K for 0.5 h to improve the performance of the device [22], the TFTs were characterized at room temperature by Keithley 230 voltage source and Keithley 617 electrometer. Since the thicknesses of the nc-Si:H films used in the TFTs are lower than that of the test films for optical-electrical investigation, the I-V measurements were also performed from drainsource contacts to find the channel layer resistivities.…”

Influence of crystalline volume fraction on the performance of high mobility microcrystalline silicon thin-film transistors

“…In order to improve the device behavior all transistors were annealed at an elevated temperature of 150°C for 30 min under ambient conditions. A detailed description of the influence of thermal annealing on the device characteristics is given elsewhere [12]. In this study only transistors with a channel length of 200 lm were investigated as the influence of drain and source contact resistance on the device parameters is reduced for long channel transistors [13].…”