High-quality, deterministic parallel placement for FPGAs on commodity hardware

Ludwin, Adrian; Betz, Vaughn; Padalia, Ketan

doi:10.1145/1344671.1344676

Cited by 54 publications

(58 citation statements)

References 18 publications

(42 reference statements)

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“…However, with multi-core processors becoming ubiquitous, parallel CAD algorithms are now a necessity. As evidence, the FPGA companies have begun to parallelize their CAD software, and Altera has recently published their efforts on parallelizing the simulated-annealing-based placement phase of the Quartus CAD software [2]. Analytical placement has also been parallelized by Chan and Schlag [3], targeting a network-based computing environment.…”

Section: A Conventional Parallelizationmentioning

confidence: 99%

“…The result of placement should be the same given the same initial seed, and regardless of the number threads. This constraint has been given the name serial equivalence by previous work [2]. While our implementation is currently not serially equivalent, this section discusses modifications to TVPR in order to achieve serial equivalence.…”

Section: Supporting Serial Equivalencementioning

confidence: 99%

“…The implementation we report results for in this paper is not serially equivalent [2], and consequently, comparing the performance against the sequential version must be done carefully. VPR's simulated annealing schedule is dynamic 1 , therefore our implementation, since it is not deterministic, can follow a different path to convergence each time it is run, even when given the same initial random seed.…”

Section: Circuitmentioning

confidence: 99%

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Parallelizing FPGA placement using Transactional Memory

Birk

Steffan

Anderson

2010

2010 International Conference on Field-Programmable Technology

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Abstract-To capitalize on the growing abundance of multicore hardware, FPGA vendors have begun to parallelize the most compute intensive algorithms in their CAD software. However, parallelization is a painstaking and hence expensive process that limits the number of algorithms that can be cost-effectively parallelized. Transactional Memory (TM) promises an easier-touse alternative to locks for critical sections in threaded codeallowing programmers to avoid deadlocks and data races, and also allowing critical sections to execute in parallel as long as they dynamically access independent data. In this paper, we present our work on using TM to parallelize simulated annealingbased placement for FPGAs. In particular, we use a software TM (TinySTM) to parallelize the placement phase of Versatile Place and Route (VPR) 5.0.2 [1]. With TM we very quickly produced a parallel and correct version of the software, allowing us to focus on incrementally tuning performance. We describe our experiences in tuning the TM system and CAD software, and the interesting algorithmic trade-offs that exist. In the end, we found that optimized transactional placement has the potential for scalable performance: our non-deterministic implementation achieves self-relative speedups over a single thread of 1.82x, 3.62x and 7.27x at 2, 4, and 8 threads respectively with little quality degradation. However, hardware support for TM is likely required to overcome the overheads of STM, as our implementation's single thread performance is 8x slower than sequential VPR.

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Section: A Conventional Parallelizationmentioning

confidence: 99%

Section: Supporting Serial Equivalencementioning

confidence: 99%

Section: Circuitmentioning

confidence: 99%

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Parallelizing FPGA placement using Transactional Memory

Birk

Steffan

Anderson

2010

2010 International Conference on Field-Programmable Technology

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“…Over the last several years, Altera has reduced the runtime of Quartus II by more than 5X through a combination of finding new CAD algorithms with better run-time and by creating parallel CAD algorithms to exploit multi-core CPUs [3]. This more than bridges the gap between the growth of FPGA capacity and CPU speeds.…”

Section: Designer Productivitymentioning

confidence: 99%

FPGA challenges and opportunities at 40nm and beyond

Betz

2009

2009 International Conference on Field Programmable Logic and Applications

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FPGA companies are amongst the earliest adopters of next-generation integrated circuit process technology, as the economics of scaling are more favorable for FPGAs than for many other technologies. Moving to advanced processes involves many challenges, including power management, device modeling, increasing I/O performance to match the computational capacity, and enabling very large designs to be completed quickly. In this paper, we highlight the economic and technological advantages of moving FPGAs to more advanced processes, and discuss the techniques Altera is using to overcome the challenges that come with process scaling.

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“…It tries to create a good quality placement from a flattened design that no longer contains any system-level information from the original design hierarchy. As the size and complexity of FPGA designs increases, SA does not scale well; in fact, the time designers are required to wait for the successful place and route of a design using commercial CAD tools is reportedly not being alleviated by the gained computing power in new work stations [2].…”

Section: Introductionmentioning

confidence: 99%

Finding System-Level Information and Analyzing Its Correlation to FPGA Placement

Gharibian

Shannon

Jamieson

2010

2010 International Conference on Field Programmable Logic and Applications

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Abstract-One of the more popular placement algorithms for Field Programmable Gate Arrays (FPGAs) is called Simulated Annealing (SA). This algorithm tries to create a good quality placement from a flattened design that no longer contains any high-level information related to the original design hierarchy. Unfortunately, placement is an NP-hard problem and as the size and complexity of designs implemented on FPGAs increases, SA does not scale well to find good solutions in a timely fashion. As modern FPGAs can be used to implement Systems-and Networks-on-Chip, designers are required to spend an increasing amount of time waiting for place and route tools to complete that is not being matched by an increase in the power of computing work stations.In this paper, we investigate if system-level information can be reconstructed from a flattened netlist and evaluate how that information is realized in terms of its locality in the final placement. If there is a strong relationship between good quality placements and system-level information, then it may be possible to divide a large design into smaller components and improve the time needed to create a good quality placement. Our preliminary results suggest that the locality property of the information embedded in the system-level HDL structure (i.e. "module", "always", and "if" statements) is greatly affected by both the designer and the design itself. A reconstructive algorithm, called affinity propagation, is also considered as a possible method of generating a meaningful coarse grain picture of the design.

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High-quality, deterministic parallel placement for FPGAs on commodity hardware

Cited by 54 publications

References 18 publications

Parallelizing FPGA placement using Transactional Memory

Parallelizing FPGA placement using Transactional Memory

FPGA challenges and opportunities at 40nm and beyond

Finding System-Level Information and Analyzing Its Correlation to FPGA Placement

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