High-precision TDC in an FPGA using a 192 MHz quadrature clock

Fries, M.D.; Williams, J.R.

doi:10.1109/nssmic.2002.1239380

Cited by 59 publications

(32 citation statements)

References 2 publications

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“…There have been previous efforts to perform the timing pickoff in the FPGA. One way is to utilize the increasing clock frequencies to perform a timeto-digital conversion [6]. This method still requires an analog comparator, and may be limited by the complexity of using fast clocks on FPGAs.…”

Section: Timingmentioning

confidence: 99%

“…This method still requires an analog comparator, and may be limited by the complexity of using fast clocks on FPGAs. Another method is to use signal processing to achieve precisions below the sampling time interval [6]. While this method is more complex, it has the advantage of using lower frequency components, which are cheaper, lower power, and make printed circuit board design simpler.…”

Section: Timingmentioning

confidence: 99%

See 1 more Smart Citation

Fpga-based data acquisition system for a positron emission tomography (PET) scanner

Haselman

Miyaoka

Lewellen

et al. 2008

Proceedings of the 16th International ACM/SIGDA Symposium on Field Programmable Gate Arrays

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Section: Timingmentioning

confidence: 99%

Section: Timingmentioning

confidence: 99%

Fpga-based data acquisition system for a positron emission tomography (PET) scanner

Haselman

Miyaoka

Lewellen

et al. 2008

Proceedings of the 16th International ACM/SIGDA Symposium on Field Programmable Gate Arrays

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“…7,8,9,10,11 On the other hand, digital interpolation uses a gate delay to estimate the fractional clock cycles. 12,13,14,15,16,17,18,19,20 A simple TDC consists of a high frequency clock and a counter incremented at each clock edge. In such a case, the resolution is limited by the use of the reference clock frequency.…”

Section: Introductionmentioning

confidence: 99%

Time-to-digital converter based on analog time expansion for 3D time-of-flight cameras

Tanveer

Nissinen

et al. 2014

SPIE Proceedings

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This paper presents an architecture and achievable performance for a time-to-digital converter, for 3D time-offlight cameras. This design is partitioned in two levels. In the first level, an analog time expansion, where the time interval to be measured is stretched by a factor k, is achieved by charging a capacitor with current I, followed by discharging the capacitor with a current I k . In the second level, the final time to digital conversion is performed by a global gated ring oscillator based time-to-digital converter. The performance can be increased by exploiting its properties of intrinsic scrambling of quantization noise and mismatch error, and first order noise shaping. The stretched time interval is measured by counting full clock cycles and storing the states of nine phases of the gated ring oscillator. The frequency of the gated ring oscillator is approximately 131 MHz, and an appropriate stretch factor k, can give a resolution of ≈ 57 ps. The combined low nonlinearity of the time stretcher and the gated ring oscillator-based time-to-digital converter can achieve a distance resolution of a few centimeters with low power consumption and small area occupation. The carefully optimized circuit configuration achieved by using an edge aligner, the time amplification property and the gated ring oscillator-based time-to-digital converter may lead to a compact, low power single photon configuration for 3D time-of-flight cameras, aimed for a measurement range of 10 meters.

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“…Many groups have exploited the use of FPGAs for pulse processing in scanner electronics [e.g, [6][7][8][9]. In our own laboratory, the FPGAs are routinely used for pulse integration [1,12] and we are developing implementations for statistical event localization [2] and timing [5].…”

Section: Introductionmentioning

confidence: 99%

Design of a second generation firewire based data acquisition system for small animal PET scanners

Lewellen

Miyaoka

MacDonald

et al. 2008

2008 IEEE Nuclear Science Symposium Conference Record

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The University of Washington developed a Firewire based data acquisition system for the MiCES small animal PET scanner. Development work has continued on new imaging scanners that require more data channels and need to be able to operate within a MRI imaging system. To support these scanners, we have designed a new version of our data acquisition system that leverages the capabilities of modern field programmable gate arrays (FPGA). The new design preserves the basic approach of the original system, but puts almost all functions into the FPGA, including the Firewire elements, the embedded processor, and pulse timing and pulse integration. The design has been extended to support implementation of the position estimation and DOl algorithms developed for the cMiCE detector module. The design is centered around an acquisition node board (ANB) that includes 65 ADC channels, Firewire 1394b support, the FPGA, a serial command bus and signal lines to support a rough coincidence window implementation to reject singles events from being sent on the Firewire bus. Adapter boards convert detector signals into differential paired signals to connect to the ANB.

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High-precision TDC in an FPGA using a 192 MHz quadrature clock

Cited by 59 publications

References 2 publications

Fpga-based data acquisition system for a positron emission tomography (PET) scanner

Fpga-based data acquisition system for a positron emission tomography (PET) scanner

Time-to-digital converter based on analog time expansion for 3D time-of-flight cameras

Design of a second generation firewire based data acquisition system for small animal PET scanners

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