Design of a second generation firewire based data acquisition system for small animal PET scanners

Abstract

The University of Washington developed a Firewire based data acquisition system for the MiCES small animal PET scanner. Development work has continued on new imaging scanners that require more data channels and need to be able to operate within a MRI imaging system. To support these scanners, we have designed a new version of our data acquisition system that leverages the capabilities of modern field programmable gate arrays (FPGA). The new design preserves the basic approach of the original system, but puts almost all functions into the FPGA, including the Firewire elements, the embedded processor, and pulse timing and pulse integration. The design has been extended to support implementation of the position estimation and DOl algorithms developed for the cMiCE detector module. The design is centered around an acquisition node board (ANB) that includes 65 ADC channels, Firewire 1394b support, the FPGA, a serial command bus and signal lines to support a rough coincidence window implementation to reject singles events from being sent on the Firewire bus. Adapter boards convert detector signals into differential paired signals to connect to the ANB.

Evolution of the design of a second generation FireWire based data acquisition system

“…The variety of topologies that can be supported were discussed in an earlier conference record [10]. What was not apparent in [10] is that the card is not restricted to the use of FireWire.…”

“…What was not apparent in [10] is that the card is not restricted to the use of FireWire. The pinouts on the existing card for the FireWire connectors also supports a range of ethernet connectors - both copper and optical.…”

“…The outgoing FireWire signals, the master clock in, the event present and event accept control lines [10], a SPI bus for command/control from the maser controller, and the power are all on the right side of the card as pictured in Figure 8. When cooled air is required for operation (such as in our MRI insert scanner designs), the air is introduced along the bottom edge of the card and removed along the top edge of the card assuring good flow across the FPGA heat sink and the memories.…”

Evolution of the design of a second generation FireWire based data acquisition system

“…As we reported previously, the basic system design is built around a multi-purpose board design -the acquisition node board (ANB) -and we use the term Phase II electronics to describe the entire development effort [10]. We have separated the electronics design into two major subsystems analog and digital.…”

Development of a data acquisition architecture with distributed synchronization for a Positron Emission Tomography system with integrated front-end.

“…5.1b): In this case, the communication interface between the subevent timestamping nodes and the event builder is a shared transmission medium such as a data bus [344][345][346]. This allows a relatively cheap implementation of distributed coincidence detection with low latency, as timestamping nodes may broadcast the timestamps corresponding to each detected subevent so every module can detect the coincidences it is involved in, build the associated event and send it to the top node.…”