High-Performance VLSI Architecture of Decision Feedback Equalizer for Gigabit Systems

Abstract

This brief addresses the design of a decision feedback equalizer (DFE) for gigabit throughput rate. It is well known that the feedback loop in a DFE limits an upper bound of the achievable speed. For a -tap feedbackward filter (FBF) and -pulse amplitude modulation, Parhi (1991) and Kasturia and Winters (1991) reformulated the FBF as a ( ) -to-1 multiplexer. Due to the reformulation, the overhead of extra adders and extra multiplexers are as large as ( ) . The required hardware overhead should be more severe when the DFE is implemented in parallel.In this brief, we propose two new approaches to implement the DFE when gigabit throughput rate is desired. The first approach is partial precomputation scheme, which can trade-off between hardware complexity and computational speed. The second approach is two-stage pre-computation scheme, which can be applied to higher speed applications. In the later case, we can reduce the hardware overhead to about 2( ) (2) times of [1], [2], and the iteration bound is) multiplexer-delays, where is the wordlength of weight coefficient of a FBF. We demonstrate the proposed architectures by apply it to the 10 Gbase-LX4 optical communication systems.

A Low-Complexity Decision Feedforward Equalizer Architecture for High-Speed Receivers on Highly Dispersive Channels

“…A comparison of the complexity for -PAM is shown in Table 3. We observe that the DFFE still provides a significant reduction of complexity with respect to the DFE architectures [7,9]. (In -PAM, multiplication operations are achieved by using − 1 2-to-1 muxes.)…”

“…The number of adders for the DFFE was estimated assuming that the basic building block is a twoinput adder. Table 2 presents a comparison of the complexity of the DFFE with the DFE architectures proposed in [4,7,9,10]. The numbers of adders and 2-to-1 multiplexers for the parallel DFE schemes were extracted from [4,7,9], while the number of registers was estimated based on their architectures.…”

“…However, they are not considered for a speed comparison as a result of their prohibitive high implementation complexity in the presence of channels with high ISI ( ≫ 1). On the other hand, the critical path of the less complex DFE solution proposed in [7] is given by DFE− [7] ≈ (1/( /2+1)) add +log 2 ( ) mux for -PAM, where mux and add are the multiplexer and adder delays, respectively. Note that DFE− [7] is independent of the channel memory .…”

“…Some algorithms to deal with the drawbacks of the DFE in high-speed applications and parallel processing have been proposed by [4][5][6][7][8][9][10][11][12]. For example, parallel DFE architectures based on look-ahead pipelined multiplexer loops have been introduced in [6,7].…”

“…For example, parallel DFE architectures based on look-ahead pipelined multiplexer loops have been introduced in [6,7]. These architectures can mitigate the speed limitation of feedback loops by using nested multiplexer loops where the implementation is reported in [10].…”