This brief addresses the design of a decision feedback equalizer (DFE) for gigabit throughput rate. It is well known that the feedback loop in a DFE limits an upper bound of the achievable speed. For a -tap feedbackward filter (FBF) and -pulse amplitude modulation, Parhi (1991) and Kasturia and Winters (1991) reformulated the FBF as a ( ) -to-1 multiplexer. Due to the reformulation, the overhead of extra adders and extra multiplexers are as large as ( ) . The required hardware overhead should be more severe when the DFE is implemented in parallel.In this brief, we propose two new approaches to implement the DFE when gigabit throughput rate is desired. The first approach is partial precomputation scheme, which can trade-off between hardware complexity and computational speed. The second approach is two-stage pre-computation scheme, which can be applied to higher speed applications. In the later case, we can reduce the hardware overhead to about 2( ) (2) times of [1], [2], and the iteration bound is) multiplexer-delays, where is the wordlength of weight coefficient of a FBF. We demonstrate the proposed architectures by apply it to the 10 Gbase-LX4 optical communication systems.
In this paper, a prototype design of a dual-mode Viterbi/turbo decoder for 3rd generation wireless communication systems is proposed. By merging some similar modules in both the Viterbi decoder and the log-MAP turbo code decoder, we built one dual-mode decoder with both of these two functions. When the decoder operates in the turbo mode, early-termination control of the iteration process can reduce the power consumption without influencing the decoding accuracy. Besides, in order to conform to the CDMA2000 standard, our decoder can also perform as a reconfigurable Viterbi decoder. That is, our design meets the requirement of the multi generator polynomial convolutional code specification. The design provides an integrated FEC kernel for modern communication systems.
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