High Performance Ternary Multiplier Using CNTFET

Design and CNFET Implementation of the GDI Based Ternary Prefix Adders

“…The three input XOR gate also utilized to construct the TFA [M3] [30]. The ternary adder [M4] also used to construct the ternary multiplier [31]. These methodologies are operated in the binary based logic.…”

“…Table 5 -Table 9 depicts the measurement of current, power, energy, delay and PDP of the different adder topologies. 13.549u 16.577u 12.514u M3 [30] 1.2894n 1.3343n 1.4678n M4 [31] 486.88p 317.91p 353.66p M5A [32] 715.15p 849.18p 814.41p M5B [32] 57.921n 66.425n 75.034n MTPA1 [19] 922.6p 929.57p 950.01p MTPA2 [19] 2.8378n 2.8932n 2.9545n MTPA3 [19] 2.0199n 2.0586n 2.102n MTPA4 [19] 423.62p 606.41p 1.7021n MTPA5 [19] 8.032n [29] 11.673u 14.919u 12.514u M3 [30] 1.0315n 1.2008n 1.4678n M4 [31] 389.51p 396.12p 353.66p M5A [32] 572.12p 764.26p 814.41p M5B [32] 46.337n 59.783n 75.034n MTPA1 [19] 729.81p 836.61p 950.01p MTPA2 [19] 2.2703n 2.6039n 2.9545n MTPA3 [19] 1.6159n 1.8527n 2.102n MTPA4 [19] 422.3p 640.44p 15.984n MTPA5 [19] 6.4n [29] 889.32f 923.92f 768.66f M3 [30] 51.575a 60.042a 73.385a M4 [31] 19.475a 98.1a 102.683a M5A [32] 21.726a 30.938a 32.253a M5B [32] 2.3277f 3.0107f 3.7587f MTPA1 [19] 36.49a 41.83a 47.5a MTPA2 [19] 113.51a 130.19a 147.72a MTPA3 [19] 80.796a 92.634a 105.1a MTPA4 [19] 86.115a 97.0222a 102.99a MTPA5 [19] 97 31.098n 32.952n 33.613n M3 [30] 2.3547n 2.5072n 2.4115n M4 [31] 12.56n 15.39n 3.0693n M5A [32] 1.0039n 1.0039n 1.0039n M5B [32] 1.0031n 1.0032n 1.0032n MTPA1 [19] 41.341n 43.891n 49.875n MTPA2 [19] 39.687n 39.571n 59.853n MTPA3…”

“…The noise margin of the ternary logic is expressed in following ( 27) - (30). The minimum amount of the NM is also represented in (31).…”