Design and CNFET Implementation of the GDI Based Ternary Prefix Adders

Abstract

Ternary adders have produced more benefits compared to the binary adders (i.e.) the ternary adder occupies less amount of area as well as produces less interconnect complexity. But the CMOS implementation of the ternary adders are failed to perform the process when the channel length is taken as 32nm. At 32nm technology, the CMOS transistors are exhibited undesired effects such as SCE, mobility degradation, etc., These issues are overcome by multi-gate devices. CNFETs (Carbon Nano-tube Field Effect Transistors) are the one of the technology to work efficiently when channel length is 32nm. In this paper, CNFETs based ternary prefix adders are designed. The power consumption is the most needed requirement for the VLSI system. So, this can be achieved by reducing the number of transistors. The reduction approach is called as the GDI (Gate Diffusion Input) logic is also included in the proposed prefix adder design. The proposed adder improved by reducing the power upto 83%, Energy upto 83%, current upto 78%, delay upto 96%. Finally, the PDP (Power Delay product) also reduced by 84% compared to existing ternary adders.