High-performance sub-1 V CMOS voltage reference with low supply voltage

Thakur, Arvind; Pandey, Rishikesh; Kumar, Shireesh

doi:10.1016/j.aeue.2022.154392

Cited by 7 publications

(2 citation statements)

References 45 publications

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“…Presented VRs in [23,24] are also operated based on the subtraction of two complementary-to-absolute temperature (CTAT) currents. The ratio of currents is adjusted to yield the best TC value.…”

Section: Power Supply Ripple Rejectionmentioning

confidence: 99%

Ultra‐low line sensitivity and high PSRR sub‐threshold CMOS voltage reference

Rashtian

2023

The Journal of Engineering

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This paper presents a nanowatt CMOS voltage reference (VR) with ultra-low line sensitivity (LS) and high-power supply ripple rejection (PSRR). The proposed VR consists of two simple nanowatt two-transistor (2T) VRs. Two current mirrors are associated with these VRs. The outputs of the current mirrors have different magnitudes but the same power supply dependence slope. For this purpose, the primary 2T VR has been designed with long-channel MOSFETs, while the secondary VR utilizes medium-channel length transistors. Low dependence on the power supply variations is achieved by subtracting these two currents, whereas the subtracted current is almost independent of the power supply. The temperature coefficient (TC) minimization is achieved separately by adjusting the transistor sizes of the primary VR. Post-layout simulation is performed using 0.18 µm standard CMOS technology, which shows a nominal output voltage of 0.15 V, obtaining an average TC of 21.4 ppm/ • C over a temperature range of 0-120 • C. It achieves an excellent line sensitivity of 0.0039%/V when the supply voltage varies from 0.4 to 2 V. The dc PSRR values at 0.4 and 1 V of supply voltage are −80.1 and -114.2 dB, respectively at room temperature.

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Section: Power Supply Ripple Rejectionmentioning

confidence: 99%

Ultra‐low line sensitivity and high PSRR sub‐threshold CMOS voltage reference

Rashtian

2023

The Journal of Engineering

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“…In addition, many researchers have optimized the error amplifier and then proposed a multistage amplifier to improve the loop gain. However, this adds an extra structure and leads to an increase in power consumption [9]. The proposed reference voltage circuit exploits a high-gain class-AB OTA as the error amplifier, without buffer or more amplifier stages, but improves transient response and voltage accuracy, effectively.…”

Section: Circuit Design and Implementationmentioning

confidence: 99%

A Reference Voltage Circuit Applied in High Precision Delta-Sigma ADC

Duan,

Wang,

Duan

2023

J. Phys.: Conf. Ser.

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A novel reference voltage circuit design which is applied in high-precision Delta-Sigma ADC is implemented. The proposed reference circuit exploits a high-gain class-AB OTA as the error amplifier, which improves the transient response characteristics, ensures loop stability, and does not increase additional power consumption. The design and simulation of the proposed reference voltage circuit are fabricated by SMIC.18 CMOS technology. The simulation results manifest that the temperature coefficient of the bandgap reference is 6.825 ppm/°C in the temperature range from -40°C to 125°C. The transient response of the proposed reference circuit takes about 13 ns to reach the precision demanded by the reference voltage. The Σ-Δ modulator with the designed reference voltage circuit applied has an effective number of bits (ENOB) of 18.1 bits, a signal-to-noise-ratio (SNR) of 111.2 dB, and a signal-to-noise-plus-distortion (SNDR) of 110.9 dB at 1MHz sampling frequency and 625 Hz input signal.

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