A 79 pW, 106 ppm/°C NMOS-only current reference with leakage current isolation based on body bias technique

Huang, Wenjian; Zeng, Yanhan; Yang, Jingci; Li, Yongfu

doi:10.1016/j.aeue.2023.154539

Cited by 5 publications

(1 citation statement)

References 21 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Operation principle of PTAT references proposed in prior art [10], [11] (in orange) and of the proposed CWT reference (in blue). Analytical expression of (a) the voltage V X applied to the SCM, (b) the inversion level of M 2 , denoted as i similarities with 4T structures introduced in [14], [20]. The transistors constituting this 4T voltage reference [Fig.…”

Section: B 4t Ultra-low-power Voltage Referencementioning

confidence: 99%

A 2.5-nA Area-Efficient Temperature-Independent 176-/82-ppm/$^\circ$C CMOS-Only Current Reference in 0.11-$\mu$m Bulk and 22-nm FD-SOI

Lefebvre,

Bol

2024

IEEE J. Solid-State Circuits

View full text Add to dashboard Cite

Internet-of-Things (IoT) applications require nW-power current references that are robust to process, voltage and temperature (PVT) variations, to maintain the performance of IoT sensor nodes in a wide range of operating conditions. However, nA-range current references are rarely area-efficient due to the use of large gate-leakage transistors or resistors, which occupy a significant silicon area at this current level. In this paper, we introduce a nA-range constant-with-temperature (CWT) current reference, relying on a self-cascode MOSFET (SCM) biased by a four-transistor ultra-low-power voltage reference through a single-transistor buffer. The proposed reference includes a temperature coefficient (TC) calibration mechanism to maintain performance across process corners. In addition, as the proposed design relies on the body effect, it has been fabricated and measured in 0.11-µm bulk and 22-nm fully-depleted silicon-on-insulator (FD-SOI) to demonstrate feasibility in both technology types. On the one hand, the 0.11-µm design consumes a power of 16.8 nW at 1.2 V and achieves a 2.3-nA current with a line sensitivity (LS) of 2.23 %/V at 25 • C and a TC of 176 ppm/ • C at 1.2 V from -40 to 85 • C. On the other hand, the 22-nm design consumes a power of 16.3 nW at 1.5 V and achieves a 2.5-nA current with a 1.53-%/V LS at 25 • C and an 82-ppm/ • C TC at 1.5 V from -40 to 85 • C. Thanks to their simple architecture, the proposed references achieve a silicon area of 0.0106 mm 2 in 0.11 µm and 0.0026 mm 2 in 22 nm without compromising other figures of merit, and are thus competitive with state-of-the-art CWT references operating in the same current range.

show abstract