High Performance SiGe Body-On-Insulator (BOI) FinFET Fabricated on Bulk Si Substrate Using Ge Condensation Technique

Ren, Zhexuan; An, Xia; Zhang, Bingxin; Sun, Shuang; Gao, Fei; Li, Ming; Zhang, Xing; Huang, Ru

doi:10.1109/led.2020.3007333

Cited by 10 publications

(4 citation statements)

References 17 publications

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“…The value of β, for a given set of device parameters, can be easily extracted by the fitting equation ( 26) with V th extracted through the model, i.e. equation (24). The value of α can be evaluated from the subthreshold swing.…”

Section: Resultsmentioning

confidence: 99%

Ultra-low-power subthreshold logic with germanium junctionless transistors

Shrivas

Jaiswal

Semwal

et al. 2021

Semicond. Sci. Technol.

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The present work investigates the suitability of Ge junctionless (JL) transistors for subthreshold logic applications. Considering that Ge exhibits a higher degree of short channel effects due to its higher permittivity, a semi-analytical model is first developed to capture the potential distribution and electron concentration in double gate (DG) Ge JL transistors with underlap regions for subthreshold operation. The model accurately predicts threshold voltage, drain-induced barrier lowering and subthreshold swing in Ge-based DG JL transistors. The work is extended to evaluate the subthreshold drain current for n-type and p-type DG Ge JL devices and the approach is adapted to extract three key technology-dependent parameters for ultra-low-power (ULP) (subthreshold) operation. The technology-dependent parameters are then utilized to evaluate key performance metrics of a subthreshold inverter. The upper and lower output voltage swing values, logic threshold voltage, and gain of the subthreshold inverter agree reasonably well with the developed modeling framework. The impact of technology downscaling, from a 5 nm to 0.7 nm node, on the performance of DG Ge JL subthreshold inverter is investigated, and possible options to enhance gain are outlined. Transient analysis highlighting NOT, NAND and NOR logic functionality with subthreshold Ge JL transistors has been investigated. Apart from base device and circuit assessment, the work also investigates the sensitivity of key metrics on physical transistor dimensions, supply voltage and temperature. The work showcases the potential benefits of optimally designed ULP n-type and p-type metal-oxide-semiconductor Ge JL devices for subthreshold logic applications.

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Section: Resultsmentioning

confidence: 99%

Ultra-low-power subthreshold logic with germanium junctionless transistors

Shrivas

Jaiswal

Semwal

et al. 2021

Semicond. Sci. Technol.

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“…The above‐mentioned DC–DC boost converter circuits designed using CMOS technology show peak PCE greater than 30%. However, the performance of CMOS technology‐based DC–DC boost converter degrades due to presence of short channel effects (SCE) for technology nodes below 20 nm 26–32 . One of the tactics to deal with this issue could be the replacement of MOSFET device with FinFET device.…”

Section: Introductionmentioning

confidence: 99%

“…However, the performance of CMOS technology-based DC-DC boost converter degrades due to presence of short channel effects (SCE) for technology nodes below 20 nm. [26][27][28][29][30][31][32] One of the tactics to deal with this issue could be the replacement of MOSFET device with FinFET device. The FinFET device has better controllability over the channel current due to its 3-dimensional gate trap over the channel.…”

Section: Introductionmentioning

confidence: 99%

Low‐power FinFET based boost converter design using dynamic threshold body biasing technique

Sharma,

Thakur,

Elangovan

et al. 2023

Int J Numerical Modelling

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The recent development in the field of sustainable energy solution for ultra‐low power application is attracting the attention of researchers. This paper is themed on the boosting of input harvested voltage from micro thermo‐electric generator to an appropriate output voltage level. This research proposed an optimized DC–DC boost converter design comprising of cross‐coupled FinFET based LC resonant oscillator and FinFET three‐stage charge pump circuit. The design utilizes the dynamic threshold body biasing technique to control the threshold voltage of FinFET switches and enhance the performance in sub‐threshold region. This design succeeded in achieving 29.25% peak power conversion efficiency to generate 438 mV output voltage from 96 mV minimum input voltage while consuming 344 nW of power only. Further, the proposed boost converter shows peak voltage conversion efficiency of 53.51% and settling time of 121 μS for 1% band. The performance of proposed boost converter observed for rigorous process, temperature and load variations is within acceptable limits. In contrast to MOSFET technology, the adopted 18 nm FinFET technology make the proposed design excellent to tackle the challenges of short channel effects in ultra‐low power application.

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“…These devices are futuristic candidates for developing digital circuits, processors, memories, and computing devices for internet of things (IoT)-based infrastructure and health industry [3,[7][8][9]. The existing MOSFET technology suffers from presence of short channel effects (SCE) and high sensitivity towards process, voltage, and temperature (PVT) variations in technology nodes below 20 nm [10][11][12][13][14][15]. To deal with issue, the next-generation field effect transistors (FETs) like FINFETs, tunnel FETs (TFETs), carbon nanotube FETs (CNTFETs), and graphene nanoribbon FETs (GNRFETs) could be used in place of MOSFETs for lower technology nodes.…”

Section: Introductionmentioning

confidence: 99%

Characterisation of graphene nano-ribbon field effect transistor and design of high performance PPN 12T GNRFET Full adder

Elangovan,

Sharma,

Sachdeva

2023

Phys. Scr.

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Owing to balanced electrical properties of graphene nanoribbon field effect transistors (GNRFETs) they a suitable next-generation devices for designing high performance circuits. However, as the fabrication for GNRFETs is at premature stage the performance of GNRFET device need to be explored with variation in its parameters. This article comprehensively analyses the impact of variations in GNRFET parameters on its threshold voltage, subthreshold swing and Ion/Ioff ratio. As an application example high performance PPN 12 T full adder is proposed using GNRFET device. The proposed full adder circuit shows dynamic power, propagation delay, and low power-delay product of 43.3 nW, 0.47 pS and 0.02 x 10-18 J, respectively using 0.7 V supply voltage. The performance of proposed full adder is compared with five previously proposed full adders using 16 nm GNRFET model in HSPICE simulation tool. Further, the impact of the GNRFET parameters on performance of proposed FA is investigated. A study of this nature is expected to improve performance of computing systems used in internet of things (IoT)-based infrastructure and health industry which demand for high performance next generation devices-based circuits.

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High Performance SiGe Body-On-Insulator (BOI) FinFET Fabricated on Bulk Si Substrate Using Ge Condensation Technique

Cited by 10 publications

References 17 publications

Ultra-low-power subthreshold logic with germanium junctionless transistors

Ultra-low-power subthreshold logic with germanium junctionless transistors

Low‐power FinFET based boost converter design using dynamic threshold body biasing technique

Characterisation of graphene nano-ribbon field effect transistor and design of high performance PPN 12T GNRFET Full adder

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