High-Performance Polycrystalline Silicon TFT on the Structure of a Dopant-Segregated Schottky-Barrier Source/Drain

Choi, Sung-Jin; Han, Jin−Woo; Kim, Sungho; Moon, Dong‐Il; Jang, Moongyu; Choi, Yang‐Kyu

doi:10.1109/led.2009.2038348

Cited by 15 publications

(5 citation statements)

References 16 publications

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“…This indicates the source/drain region of SiNW channel was completed transformed to NiSi phase and the Schottky barrier interface between NiSi source/drain and Si NW channel are inherently formed. 23,24 Fig. 2b shows the cross sectional TEM micrograph of SiNW channel, a rectangular shape of SiNW with multi-layer thick of SiO 2 /Si 3 N 4 /SiO 2 /poly-Si gate were clearly verified.…”

Section: Resultsmentioning

confidence: 84%

Ambipolar Conduction Behavior on High Performance Schottky Barrier Source/Drain Gate-All-Around Si Nanowire Nonvolatile SONOS Memory

Chang

Lee

et al. 2012

ECS J. Solid State Sci. Technol.

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A Novel structure and high performance of the Schottky barrier source/drain gate-all-around (GAA) poly-Si nanowire (SiNW) nonvolatile silicon-oxide-nitride-oxide-silicon (SONOS) memory cell is reported with transistor characteristics, efficient programming/erasing, and reliability. The non-uniform thermal stress distribution on SiNW channel due to thermal insulation from the substrate by the buried oxide layer could affect carrier transport behavior. Under a high lateral electric field, the impact ionization is found since a large lateral field enhances carrier velocity. As gate voltage increases, the difference of the drain current between higher and room temperatures can be reduced because a high gate field lowers the Schottky barrier height of source/drain to ensure a strong hot-carriers generation. In particular, the ambipolar conduction of the Schottky barrier source/drain devices promotes the amount of hot-electron injecting programming by positive gate voltage, whereas the Schottky barrier enhances the generation of hot-holes at negative gate voltage to carry out erasure. The proposed Schottky barrier SONOS memory device provides low-voltage and high efficiency programming/erasing without apparent degradation of data retention and 10-K cycling endurance.As the scaling technology down to the 22 nm node and beyond, the planar architectures in very-large-scale integration (VLSI) have shown electrical degradation. 1,2 This stimulates researchers to develop novel structures such as fin-shaped field-effect transistors FETs (FinFET), tunnel FET, nanowire FET, and silicon-on-insulator (SOI) FET as alternative for future 22 nm devices. 3-5 Furthermore, due to conventional ions diffused source/drain (S/D) definition used in MOS-FET structures, the short channel effect becomes severe and obstructs MOSFET and memory cell continued aggressively scaling. Therefore, the nonplanar device structures incorporated better electrostatic control of channel potential that have emerged from the semiconductor industry to be the most attracted candidate to conquer the limitation of continued shrinkage in conventional MOSFETs and improve planar type of nonvolatile memory performance. 6-9 Among them, the adoption of FinFET SONOS memory shows potential for scaling capability and also represents charge-trap silicon-oxide-nitride-oxide-silicon (SONOS) memory with superior gate-control capability and local field enhancement. It can apparently improve the short-channel effect and dramatically enhance programming and erasing efficiency. 10-12 In particular, silicon nitride (SiN) acted as a storage node that resists, few electrons escape because charges are stored at a deep trap level, and, thus, the retention issue is immune to tunnel oxide defects. 13,14 Recently, a novel structure, the gate-all-around (GAA) silicon nanowire (SiNW) MOSFET proposed similar advantages to Fin-FET SONOS. FinFET SONOS has emerged from nano-scale devices due to compatible VLSI process flow and excellent electrical results. 15,16 The benefit of a smaller diamete...

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Section: Resultsmentioning

confidence: 84%

Ambipolar Conduction Behavior on High Performance Schottky Barrier Source/Drain Gate-All-Around Si Nanowire Nonvolatile SONOS Memory

Chang

Lee

et al. 2012

ECS J. Solid State Sci. Technol.

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“…In particular, we have shown that parasitic resistance effects, related to residual damage induced by ion implantation and not annealed by the laser, can severely limit the advantages of downscaling L on the on-current. Recently, formation of NiSi [25] or raised SiGe [26] source-drain contacts have been proposed to reduce the parasitic resistance. Output characteristics are influenced by the kink effect which has a severe impact on the output conductance of short channel TFTs.…”

Section: Discussionmentioning

confidence: 99%

(Invited) Downscaling Issues in Polycrystalline Silicon TFTs

Fortunato¹,

Cuscunà

Gaucci

et al. 2010

ECS Trans.

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Future system-on-panel applications require further performance improvement of circuits based on polycrystalline silicon thin film transistors (TFTs). The biggest leverage in circuit performance can be obtained by reducing channel length from the typical current values of 3-6Pm to 1Pm, or less. Therefore, short channel effects in scaled down polysilicon TFTs will have to be controlled in order to allow proper operation of the circuits. In this work we review a number of specific aspects of the electrical characteristics of short channel devices (channel lengths down to 0.4 Pm) combining electrical characteristics measurements and two-dimensional numerical simulations.

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“…Rather than use a midband gap oxide, a Korean group then explored using Pt silicide for the p-devices and Er silicide for the n-devices [191,192], demonstrating high on/off ratios and low leakages, but at the cost of temperatures up to 500 °C. The use of Ni silicide and dopant segregation was used to realize devices down to channel lengths of 0.1 μm with fabrication temperatures of 400 °C [193]. Most recently, SBTFTs with processing temperatures down to 350 °C, suitable for polymeric substrates using Cr and Ti barriers but only exhibiting on/off ratios of 5 × 10 3 [194].…”

Section: Opportunities Of Sb Devices For Ubiquitous Electronicsmentioning

confidence: 99%

The Schottky barrier transistor in emerging electronic devices

et al. 2023

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This paper explores how the Schottky barrier (SB) transistor is used in a variety of applications and material systems. A discussion of SB formation, current transport processes, and an overview of modeling are first considered. Three discussions follow, which detail the role of SB transistors in high performance, ubiquitous and cryogenic electronics. For high performance computing, the SB typically needs to be minimized to achieve optimal performance and we explore the methods adopted in carbon nanotube technology and two-dimensional electronics. On the contrary for ubiquitous electronics, the SB can be used advantageously in source-gated transistors and reconfigurable FETs for sensors, neuromorphic hardware and security applications. Similarly, judicious use of a SB can be an asset for applications involving Josephson junction FETs.

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High-Performance Polycrystalline Silicon TFT on the Structure of a Dopant-Segregated Schottky-Barrier Source/Drain

Cited by 15 publications

References 16 publications

Ambipolar Conduction Behavior on High Performance Schottky Barrier Source/Drain Gate-All-Around Si Nanowire Nonvolatile SONOS Memory

Ambipolar Conduction Behavior on High Performance Schottky Barrier Source/Drain Gate-All-Around Si Nanowire Nonvolatile SONOS Memory

(Invited) Downscaling Issues in Polycrystalline Silicon TFTs

The Schottky barrier transistor in emerging electronic devices

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