High-Performance Poly-Si Thin-Film Transistor With High-&lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$k$ &lt;/tex-math&gt;&lt;/inline-formula&gt; ZrTiO&lt;sub&gt;4&lt;/sub&gt; Gate Dielectric

Park, Jae Hyo; Jang, Gil Su; Kim, Hyung Yoon; Lee, Sol Kyu; Joo, Seung Ki

doi:10.1109/led.2015.2462745

Cited by 22 publications

(5 citation statements)

References 16 publications

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“…were developed and a steep SS was successfully realized, reaching up to 60 mV/dec (Fig. 6)666768697071. However, a larger dielectric constant is needed to reach 60 mV/dec.…”

Section: Resultsmentioning

confidence: 99%

Sub-kT/q Subthreshold-Slope Using Negative Capacitance in Low-Temperature Polycrystalline-Silicon Thin-Film Transistor

Park

Jang

Kim

et al. 2016

Sci Rep

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Realizing a low-temperature polycrystalline-silicon (LTPS) thin-film transistor (TFT) with sub-kT/q subthreshold slope (SS) is significantly important to the development of next generation active-matrix organic-light emitting diode displays. This is the first time a sub-kT/q SS (31.44 mV/dec) incorporated with a LTPS-TFT with polycrystalline-Pb(Zr,Ti)O3 (PZT)/ZrTiO4 (ZTO) gate dielectrics has been demonstrated. The sub-kT/q SS was observed in the weak inversion region at −0.5 V showing ultra-low operating voltage with the highest mobility (250.5 cm2/Vsec) reported so far. In addition, the reliability of DC negative bias stress, hot carrier stress and self-heating stress in LTPS-TFT with negative capacitance was investigated for the first time. It was found that the self-heating stress showed accelerated SS degradation due to the PZT Curie temperature.

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“…were developed and a steep SS was successfully realized, reaching up to 60 mV/dec (Fig. 6)666768697071. However, a larger dielectric constant is needed to reach 60 mV/dec.…”

Section: Resultsmentioning

confidence: 99%

Sub-kT/q Subthreshold-Slope Using Negative Capacitance in Low-Temperature Polycrystalline-Silicon Thin-Film Transistor

Park

Jang

Kim

et al. 2016

Sci Rep

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“…Therefore, figure 10 gives the simulation results of dependence of BV and R on,sp on the permittivity ε D . The permittivity values of 25, 50, 80, and 100 are corresponding to the high-k materials of HfO 2 , [17] ZrTiO 4 , [18] TiO 2 , [19] 10. Dependences of BV and R on,sp on ε D for the HKSD devices with different L d .…”

Section: Optimizations and Discussionmentioning

confidence: 99%

Numerical and analytical investigations for the SOI LDMOS with alternated high-k dielectric and step doped silicon pillars*

Yao¹,

Guo²,

Zhang³

et al. 2020

Chinese Phys. B

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This paper presents a new silicon-on-insulator (SOI) lateral-double-diffused metal-oxide-semiconductor transistor (LDMOST) device with alternated high-k dielectric and step doped silicon pillars (HKSD device). Due to the modulation of step doping technology and high-k dielectric on the electric field and doped profile of each zone, the HKSD device shows a greater performance. The analytical models of the potential, electric field, optimal breakdown voltage, and optimal doped profile are derived. The analytical results and the simulated results are basically consistent, which confirms the proposed model suitable for the HKSD device. The potential and electric field modulation mechanism are investigated based on the simulation and analytical models. Furthermore, the influence of the parameters on the breakdown voltage (BV) and specific on-resistance (R on, sp) are obtained. The results indicate that the HKSD device has a higher BV and lower R on, sp compared to the SD device and HK device.

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“…The a-Si TFTs offer small electron mobilities (<1 cm 2 /Vs), and thus low switching speed [9]. The other hand, poly-Si TFTs are devices with high performance, but they are fabricated at higher temperatures (500-600 • C) [10][11][12], while IGZO TFTs have moderate mobilities (>10 cm 2 /Vs) and low temperature of fabrication [13]. However, this semiconductor is only used for the fabrication of n-type devices, for p-type is used a different semiconductor, such as SnO [14].…”

Section: Introductionmentioning

confidence: 99%

Analytical Drain Current Model for a-SiGe:H Thin Film Transistors Considering Density of States

et al. 2020

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Thin film transistors (TFTs) fabricated on flexible and large area substrates have been studied with great interest due to their future applications. Recent studies have developed new semiconductors such as a-SiGe:H for fabrication of high performance TFTs. These films have important advantages, including deposition at low temperatures and low pressures, and higher carrier mobilities. Due to these advantages, the a-SiGe:H films can be used in the fabrication of TFTs. In this work, we present an analytical drain current model for a-SiGe:H TFTs considering density of states and free charges, which describes the current behavior at sub-and above- threshold region. In addition, 2D numerical simulations of a-SiGe:H TFTs are developed. The results of the analytical drain current model agree well with those of the 2D numerical simulations. For all characteristics of the drain current curves, the average absolute error of the analytical model is close to 5.3%. This analytical drain current model can be useful to estimate the performance of a-SiGe:H TFTs for applications in large area electronics.

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High-Performance Poly-Si Thin-Film Transistor With High-<inline-formula> <tex-math notation="LaTeX">$k$ </tex-math></inline-formula> ZrTiO<sub>4</sub> Gate Dielectric

Cited by 22 publications

References 16 publications

Sub-kT/q Subthreshold-Slope Using Negative Capacitance in Low-Temperature Polycrystalline-Silicon Thin-Film Transistor

Sub-kT/q Subthreshold-Slope Using Negative Capacitance in Low-Temperature Polycrystalline-Silicon Thin-Film Transistor

Numerical and analytical investigations for the SOI LDMOS with alternated high-k dielectric and step doped silicon pillars*

Analytical Drain Current Model for a-SiGe:H Thin Film Transistors Considering Density of States

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