Numerical and analytical investigations for the SOI LDMOS with alternated high-k dielectric and step doped silicon pillars*

Yao, Jiafei; Guo, Yufeng; Zhang, Zhenyu; Yang, Kemeng; Zhang, Maolin; Xia, Tian

doi:10.1088/1674-1056/ab6960

Cited by 8 publications

(5 citation statements)

References 20 publications

(37 reference statements)

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“…It can be seen when L increase from 0.3 μm to 0.55μm, the depletion region increase obviously , while the depletion boundary keeps nearly no change from L= 0.55μm to L=0.65μm. Since the current path length , which is discussed in Section II, part C, is proportional to the depletion region, the result consists of equation (2)(3)(4)(5)(6). The reason for limitation at L=0.55μm is due to depletion region limitation, which is considered related to drift/body concentration, and another possible reason is that the current path length is not circular again at higher drift region.…”

Section: B Field Plate Length-l Effectsmentioning

confidence: 99%

Design and Simulation Optimization of an Ultra-Low Specific On-Resistance LDMOS Device

Yu,

Shao,

Chen

et al. 2024

IEEE J. Electron Devices Soc.

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The design of LDMOS (Lateral double diffused metal oxide semiconductor) devices with CFP (Contact field plate) has been of great significance in recent years, according to its advantages of low resistance and high switch efficiency. In this paper, this ultra-low , (Specific on-resistance) LDMOS device is simulated, designed, and fabricated. The effects on FOM (Figures-of-merits) characters from physical dimensions, including field plate length L, field plate thickness H, and slot contact width W, have been analyzed and discussed. The best device structure is proposed through simulation, and a related fabrication process is introduced correspondingly. Finally, the electrical measurement results show that , can achieve as low as 6.9m•mm 2 when the source-drain (Breakdown voltage) arrives at 34.1V, which is improved by 47.1% compared with conventional devices. Furthermore, the TLP (Transmission line pulse) test results indicate that the device owns an ideal SOA (Safe operation area) from both typical devices (W=10 m) and very large devices (W= 2mm). Index Terms-Contact field plate (CFP), Figures of merits (FOM), Lateral double diffusion metal oxide semiconductor (LDMOS), Specific on-resistance ( , )

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Section: B Field Plate Length-l Effectsmentioning

confidence: 99%

Design and Simulation Optimization of an Ultra-Low Specific On-Resistance LDMOS Device

Yu,

Shao,

Chen

et al. 2024

IEEE J. Electron Devices Soc.

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“…For all types of LDMOS devices with oxide field plate, such as mini-LOCOS field plate, mini-STI field plate, and high-temperature oxide field plate, the source-drain breakdown voltage can be qualitatively expressed [14] as follows:…”

Section: Theory Analysismentioning

confidence: 99%

A Process Optimization Method of the Mini-LOCOS Field Plate Profile for Improving Electrical Characteristics of LDMOS Device

Yu,

Shao,

Gao

et al. 2023

IET Circuits, Devices & Systems

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In this work, the effects of the mini-local oxidation of silicon (LOCOS) field plate’s bottom physical profile on the devices’ breakdown performance are analyzed through technology computer-aided design simulations. It is indicated that the “abrupt” bottom profile could certainly do with an optimization. This paper introduces an effective process improvement method by etching bias power adjustment and time reduction. The upgradation of the field plate physical profile has been proved by transmission electron microscope cross-section analysis. The angle for the bottom surface of mini-LOCOS field plate θ2 is improved from 11.9° to 12.6°, and the thickness ratio of Hup/Hbottom (field plate oxide thickness for the upper and bottom, respectively) is increased from 71.8% to 76.6%. Finally, the optimized laterally diffused metal oxide semiconductor devices have been fabricated, and both figure of merit curves and safe operation area curves are measured. The specific on-resistance Ron,sp could achieve as low as 11.3 mΩ mm2, while breakdown voltage BVds,max arrives at 37.4 V, which is nearly 19.3% improved.

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“…Another method is depositing the high-k dielectric into the deep trench with the integration of variable-k technology, trench gate technology, and so on; the figure of merit (FOM) of the SOI LDMOS is significantly improved, but the fabrication process is more complex [11], [12], [13]. The application of the sidewall high-k dielectric is also an effective method to modulate the lateral and vertical electric field distributions [14], [15], [16], [17]. Moreover, the assisted depletion of the sidewall high-k dielectric to the drift region reduces R on,sp obviously.…”

Section: Introductionmentioning

confidence: 99%

SOI LDMOS With High-k Multi-Fingers to Modulate the Electric Field Distributions

Yao

Sun

et al. 2023

IEEE Trans. Electron Devices

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The silicon-on-insulator (SOI) lateral doublediffused metal-oxide-semiconductor (LDMOS) with high-k multi-fingers (HKMFs) is proposed and investigated. The fingertips are distributed at specific locations to modulate the electric field distributions and improve the device performances. First, the electric field peaks formed at the fingertips could optimize the electric field distributions, which improves the breakdown voltage (BV) of the LDMOS effectively. Meanwhile, the multi-fingers are embedded into the drift region to increase the optimal drift doping concentration, which facilitates the positive conduction of the device and reduces the specific ON-resistance (R on,sp ). The simulation results show that the proposed HKMF-LDMOS with five multi-fingers increases the BV by 59.2%, reduces R on,sp by 37.8%, and improves the figure of merit (FOM) by 4.07 times when compared to the conventional LDMOS.

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Numerical and analytical investigations for the SOI LDMOS with alternated high-k dielectric and step doped silicon pillars*

Cited by 8 publications

References 20 publications

Design and Simulation Optimization of an Ultra-Low Specific On-Resistance LDMOS Device

Design and Simulation Optimization of an Ultra-Low Specific On-Resistance LDMOS Device

A Process Optimization Method of the Mini-LOCOS Field Plate Profile for Improving Electrical Characteristics of LDMOS Device

SOI LDMOS With High-k Multi-Fingers to Modulate the Electric Field Distributions

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