High-Performance p-Channel LDMOS Transistors and Wide-Range Voltage Platform Technology Using Novel p-Channel Structure

Shimamoto, Satoshi; Yanagida, Yohei; Shirakawa, Shingo; Miyakoshi, Kazuo; Oshima, Takayuki; Sakano, J.; Wada, S.; Noguchi, J.

doi:10.1109/ted.2012.2228202

Cited by 35 publications

(5 citation statements)

References 13 publications

(12 reference statements)

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Despite those wide bandgap semiconductor power devices such as SiC and GaN developing in leaps and bounds, silicon devices still occupy the largest market share due to their low cost and mature technology. A silicon-on-insulator (SOI) laterally diffused metal-oxide-semiconductor (LDMOS) devices offer the advantages of high speed, low loss, and easy integration and are widely used in power integrated circuits [1][2][3][4][5]. Breakdown voltage (BV) is an important performance indicator of the SOI LDMOS and comprises the static BV (StBV) and the transient BV (TrBV).…”

Section: Introductionmentioning

confidence: 99%

Numerical Investigation of Transient Breakdown Voltage Enhancement in SOI LDMOS by Using a Step P-Type Doping Buried Layer

et al. 2023

View full text Add to dashboard Cite

In this paper, the transient breakdown voltage (TrBV) of a silicon-on-insulator (SOI) laterally diffused metal-oxide-semiconductor (LDMOS) device was increased by introducing a step P-type doping buried layer (SPBL) below the buried oxide (BOX). Device simulation software MEDICI 0.13.2 was used to investigate the electrical characteristics of the new devices. When the device was turned off, the SPBL could enhance the reduced surface field (RESURF) effect and modulate the lateral electric field in the drift region to ensure that the surface electric field was evenly distributed, thus increasing the lateral breakdown voltage (BVlat). The enhancement of the RESURF effect while maintaining a high doping concentration in the drift region (Nd) in the SPBL SOI LDMOS resulted in a reduction in the substrate doping concentration (Psub) and an expansion of the substrate depletion layer. Therefore, the SPBL both improved the vertical breakdown voltage (BVver) and suppressed an increase in the specific on-resistance (Ron,sp). The results of simulations showed a 14.46% higher TrBV and a 46.25% lower Ron,sp for the SPBL SOI LDMOS compared to those of the SOI LDMOS. As the SPBL optimized the vertical electric field at the drain, the turn-off non-breakdown time (Tnonbv) of the SPBL SOI LDMOS was 65.64% longer than that of the SOI LDMOS. The SPBL SOI LDMOS also demonstrated that TrBV was 10% higher, Ron,sp was 37.74% lower, and Tnonbv was 10% longer than those of the double RESURF SOI LDMOS.

show abstract

Section: Introductionmentioning

confidence: 99%

Numerical Investigation of Transient Breakdown Voltage Enhancement in SOI LDMOS by Using a Step P-Type Doping Buried Layer

et al. 2023

View full text Add to dashboard Cite

show abstract

“…High-voltage Lateral Diffused Metal Oxide Semiconductor Transistor (LDMOS) is very suitable for the applications of Smart Power Integrated Circuit [1,2,3,4,5,6,7,8]. Usually, p-channel LDMOS (pLDMOS) is very attractive in the full complementary high-voltage driver ICs [9,10,11,12,13,14].…”

Section: Introductionmentioning

confidence: 99%

Simulation study of an ultra-low specific on-resistance high-voltage pLDMOS with self-biased accumulation layer

Peng

Zhao

et al. 2020

IEICE Electron. Express

View full text Add to dashboard Cite

In this letter, a high-voltage p-channel Lateral Diffused Metal Oxide Semiconductor Transistor (pLDMOS) with self-biased accumulation layer is proposed. A poly-silicon layer is formed on the thin insulator layer, which locates at the surface of the P-drift region. During on-state, an automatically obtained negative voltage is applied on the poly-silicon to induce a hole accumulation layer at the surface of the P-drift region. Therefore, the specific on-resistance (R on,sp) can be significantly reduced. Moreover, the permittivity of the gate insulator on the P-drift can be increased by selecting different insulator materials. Thus, the R on,sp can be further reduced due to more holes being accumulated at the surface of the P-drift. The simulation results shows that the R on,sp of the proposed pLDMOS can be dramatically reduced by 62.3% to 82.5% compared with that of the p-type Triple RESURF silicon limit. For the proposed pLDMOS, the transient Figure of Merit (FOM) is significantly improved by several to 10 times and the static Figure of Merit (FOM) is improved by several times compared with those of an Extended Gate pLDMOS (EG-pLDMOS) and a conventional pLDMOS.

show abstract

“…The p-channel lateral double-diffused MOSFET (LDMOS) fabricated in silicon-on-insulator (SOI) has been widely used as a high-side power switch [1]- [3]. However, under the same requirement of breakdown voltage (BV), a p-LDMOS usually has a larger specific on-resistance (R on,sp ) than an n-LDMOS.…”

Section: Introductionmentioning

confidence: 99%

A Novel p-LDMOS Additionally Conducting Electrons by Control ICs

Guo

Chen

2019

IEEE J. Electron Devices Soc.

View full text Add to dashboard Cite

A silicon-on-insulator (SOI) p-channel lateral double-diffused MOSFET (p-LDMOS), conducting not only holes but also electrons, is proposed and investigated by TCAD simulations. Its most important advantage is the greatly improved relationship between the breakdown voltage (BV) and the specific on-resistance (R on,sp ). The improvement is mainly attributed to two aspects. First, many holes can accumulate in the p-drift region in the on-state, which provides a low-resistance path for hole conduction. Second, a paralleled n-LDMOS is, meanwhile, automatically triggered to form a new path for electrons. Electrons have higher mobility than holes; thus, the device performance is further improved. Based on a simulation comparison with the previous p-LDMOS at the same BV of 300 V, the R on,sp of the proposed p-LDMOS decreased by 78% and the figure of merit (FOM) increased approximately 3.4 times. Moreover, the proposed device still has the conventional three-terminal style, and its fabrication process is compatible with CMOS technology.INDEX TERMS High-side switch, power MOSFET, silicon-on-insulator.

show abstract

High-Performance p-Channel LDMOS Transistors and Wide-Range Voltage Platform Technology Using Novel p-Channel Structure

Cited by 35 publications

References 13 publications

Numerical Investigation of Transient Breakdown Voltage Enhancement in SOI LDMOS by Using a Step P-Type Doping Buried Layer

Numerical Investigation of Transient Breakdown Voltage Enhancement in SOI LDMOS by Using a Step P-Type Doping Buried Layer

Simulation study of an ultra-low specific on-resistance high-voltage pLDMOS with self-biased accumulation layer

A Novel p-LDMOS Additionally Conducting Electrons by Control ICs

Contact Info

Product

Resources

About