High-performance low-power current sense amplifier using a cross-coupled current-mirror configuration

Hybrid-Mode SRAM Sense Amplifiers: New Approach on Transistor Sizing

“…6 evidently shows that only the proposed design can operate down to a of 0.9 V while [13], [9], and [8] cease to work at equal to 1.2, 1.3, and 1.3 V, respectively. Furthermore, at any supply voltage, the new design outperforms the rest with the smallest For example, at pF, pF and the load capacitor pF, its sensing delay is reduced to 25.8%, 20.3%, and 28.6% and its power consumption is decreased to 37.6%, 46.5%, and 24.9% as compared with [13], [9] and [8], respectively. In addition, the new SA offers an enhanced speed robustness against the varying , giving a sensitivity of only 3 ps/pF, which is better than that of the designs in [13], [9], and [8], which are 3.5, 32, and 45 ps/pF, respectively.…”

“…Fig. 6 evidently shows that only the proposed design can operate down to a of 0.9 V while [13], [9], and [8] cease to work at equal to 1.2, 1.3, and 1.3 V, respectively. Furthermore, at any supply voltage, the new design outperforms the rest with the smallest For example, at pF, pF and the load capacitor pF, its sensing delay is reduced to 25.8%, 20.3%, and 28.6% and its power consumption is decreased to 37.6%, 46.5%, and 24.9% as compared with [13], [9] and [8], respectively.…”

“…P4 and P5 act as a switch to connect the BLs to the DLs. The other 10 transistors (P6 -P10 and N1-N5) form a cross-coupled inverter which amplifies the small voltage difference on the DLs to the full CMOS logic levels [8], [9], [11], [13] and [14]. The new SA is unique in a way that it eliminated the current conveyor and transformed the normally-large BL loads (P0, P1 in Fig.…”

“…The proposed SA and other existing designs [8], [9], and [13] have been optimized and extensively simulated using Cadence's Affirma Spectre circuit simulator based on a 0.18-m CMOS process from CHRT. All four circuits were simulated using a simplified read-cycle-only two columns, two rows memory system.…”

“…The operations and read effectiveness of the existing current-mode and the proposed SAs are described in Sections II and III, respectively. Sensing delay and power consumption of the new design are graphically presented in Section IV, in comparison with the three best existing designs, namely, the charge-transfer [13], the ultralow-power [9], and the high-speed [8] designs, respectively. In Section V, we describe a modified version of the proposed SA that can operate at a low supply voltage of 0.55 V. Section VI concludes the paper.…”