High-performance floating point divide

Liddicoat, Albert A.; Flynn, Michael J.

doi:10.1109/dsd.2001.952327

Cited by 22 publications

(11 citation statements)

References 10 publications

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“…Since eight copies of an FPU are to be implemented in the case of DIVA, a good area-performance solution was one of the primary design goals. To achieve this, we adapted the multiplicative division algorithm proposed by Liddicoat and Flynn [6] [7], which computes the quotient significantly faster than other division algorithms with a relatively small hardware overhead. The multiplier in the Mu/lDiv fraction datapath is shared between multiply and divide operations and several multiply operations in the division algorithm are executed by this multiplier to reduce area.…”

Section: A Basic Blocks: Alu and Multiplier/divider Fused Unitmentioning

confidence: 99%

Design Trade-Offs in Floating-Point Unit Implementation for Embedded and Processing-In-Memory Systems

Kwon¹,

Sondeen²,

Draper³

2005 IEEE International Symposium on Circuits and Systems

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Section: A Basic Blocks: Alu and Multiplier/divider Fused Unitmentioning

confidence: 99%

Design Trade-Offs in Floating-Point Unit Implementation for Embedded and Processing-In-Memory Systems

Kwon¹,

Sondeen²,

Draper³

2005 IEEE International Symposium on Circuits and Systems

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“…Even so, it still results in a long latency to compute one operation, and the subsequent operation cannot be started until the previous operation finishes since the multiplier used in these algorithms is occupied by the several multiply operations of the algorithms. Liddicoat and Flynn [2] proposed a multiplicative division algorithm based on Taylor-series expansion as shown in Fig. 2.…”

Section: Division / Square Root Algorithmsmentioning

confidence: 99%

Floating-point division and square root using a Taylor-series expansion algorithm

Kwon¹,

Draper²

2009

Microelectronics Journal

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Section: Division / Square Root Algorithmsmentioning

confidence: 99%

Floating-point division and square root implementation using a Taylor-series expansion algorithm

Kwon

Sondeen

Draper

2008

2008 15th IEEE International Conference on Electronics, Circuits and Systems

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Abstract-Hardware support for floating-point (FP) arithmetic is an essential feature of modern microprocessor design. Although division and square root are relatively infrequent operations in traditional general-purpose applications, they are indispensable and becoming increasingly important in many modern applications. In this paper, a fused floating-point multiply/divide/square root unit based on Taylor-series expansion algorithm is presented. The implementation results of the proposed fused unit based on standard cell methodology in IBM 90nm technology exhibits that the incorporation of square root function to an existing multiply/divide unit requires only a modest 23% area increase and the same low latency for divide and square root operation can be achieved (12 cycles). The proposed arithmetic unit also exhibits a reasonably good area-performance balance.

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High-performance floating point divide

Cited by 22 publications

References 10 publications

Design Trade-Offs in Floating-Point Unit Implementation for Embedded and Processing-In-Memory Systems

Design Trade-Offs in Floating-Point Unit Implementation for Embedded and Processing-In-Memory Systems

Floating-point division and square root using a Taylor-series expansion algorithm

Floating-point division and square root implementation using a Taylor-series expansion algorithm

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