2022
DOI: 10.1109/led.2022.3152308
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High-Performance Enhancement-Mode p-Channel GaN MISFETs With Steep Subthreshold Swing

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Cited by 23 publications
(11 citation statements)
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“…To achieve the required crystal quality, typically a buffer layer consisting of several µm of GaN has to be grown first. To facilitate the 2DHG formation, an Al(In)GaN backbarrier is grown followed by the GaN channel [10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25] as sketched in figure 1(c) creating a double heterostructure (DH). However, even with a thick GaN buffer layer, it is often found that additional p-type doping either in the channel or in a supply layer above the channel is needed to compensate for the unintentional n-conductivity [2,[10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25].…”
Section: Introductionmentioning
confidence: 99%
“…To achieve the required crystal quality, typically a buffer layer consisting of several µm of GaN has to be grown first. To facilitate the 2DHG formation, an Al(In)GaN backbarrier is grown followed by the GaN channel [10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25] as sketched in figure 1(c) creating a double heterostructure (DH). However, even with a thick GaN buffer layer, it is often found that additional p-type doping either in the channel or in a supply layer above the channel is needed to compensate for the unintentional n-conductivity [2,[10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25].…”
Section: Introductionmentioning
confidence: 99%
“…The SS can be defined as the required V G to change the I DS by one order of magnitude , SS = V normalG / log 10 nobreak0em.25em⁡ I DS The I DS – V G curves for the MOSFET without and with connecting a ferroelectric capacitor were characterized during V G sweeping from −1.0 to 6.0 V and then returning to −1.0 V (see Supporting Information Figure S2a for the waveform). The mean sweeping speed of V G is ∼0.5 V/s and the step of V G sweeping is set to 0.5 mV, which is similar to previous works. ,, …”
Section: Resultsmentioning
confidence: 99%
“…The high temperature process steps of ohmic contact formation for n-HEMT (∼850 • C) and p-MOSFET (∼550 • C) are respectively designed prior to the Fluorine plasma ion implantation, which facilitates to obtain good stability of F-ion in p-MOSFET [21]. Besides, considering the possible lattice damage induced by gate recess of p-MOSFET, the wet treatment by using TMAH [22] or HCl [23] can be used to improve the recessed surface quality.…”
Section: Charge Storage Layer Simulationmentioning
confidence: 99%